Control signal training

A training method for a memory system, comprising:

• transmitting, by a controller and to a memory device, a clock signal having a clock signal period;
• transmitting, by the controller and to a device command/address interface of the memory device and via a controller command/address interface, at least a first data pattern and a second data pattern;
• transmitting, by the controller and to the memory device, a plurality of activations of a control signal, each activation of the plurality of activations having one of a plurality of phase relationships to the clock signal, the plurality of activations of the control signal to be activated for time periods that are less than the clock signal period, a first subset of the plurality of activations of the control signal causing the memory device to transmit data patterns received via the device command/address interface to the controller, a second subset of the plurality of activations of the control signal not causing the memory device to transmit data patterns;
• and
• based on the first subset and the second subset, selecting an operating phase relationship between the clock signal and the control signal.

A controller, comprising:

• a clock interface to provide a clock signal to a memory device, the clock signal to have a clock period;
• a controller command/address interface to provide a plurality of data patterns to a memory device command/address interface of the memory device;
• a control signal interface to provide a control signal to a memory device control signal interface of the memory device;
• and
• the controller to transmit to the memory device a plurality of activations of the control signal, each activation of the plurality of activations having one of a plurality of phase relationships to the clock signal, the plurality of activations of the control signal to be activated for time periods that are less than the clock period, a first subset of the plurality of activations of the control signal to cause the memory device to transmit data patterns received via the memory device command/address interface to the controller, a second subset of the plurality of activation of the control signal to not cause the memory device to transmit data patterns, and based on the first subset and the second subset, the controller to select an operating phase relationship between the clock signal and the control signal.