G11C 8/06
Address interface arrangements
Official title: Address interface arrangements, e.g. address buffers
G11C8/06 (Address interface arrangements) appears on 1,057 US grants and 864 published applications in this corpus.
Search patents in G11C- Granted patents
- 1,057
- Published applications
- 864
- Assignees
- 234
- Inventors
- 1,553
- Latest grant
- 1 Sep 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1976 | 1 | 0 |
| 1977 | 1 | 0 |
| 1978 | 1 | 0 |
| 1979 | 1 | 0 |
| 1980 | 0 | 0 |
| 1981 | 2 | 0 |
| 1982 | 2 | 0 |
| 1983 | 4 | 0 |
| 1984 | 6 | 0 |
| 1985 | 7 | 0 |
| 1986 | 2 | 0 |
| 1987 | 6 | 0 |
| 1988 | 2 | 0 |
| 1989 | 13 | 0 |
| 1990 | 10 | 0 |
| 1991 | 10 | 0 |
| 1992 | 7 | 0 |
| 1993 | 7 | 0 |
| 1994 | 19 | 0 |
| 1995 | 8 | 0 |
| 1996 | 9 | 0 |
| 1997 | 17 | 0 |
| 1998 | 20 | 0 |
| 1999 | 13 | 0 |
| 2000 | 22 | 0 |
| 2001 | 19 | 7 |
| 2002 | 27 | 17 |
| 2003 | 14 | 16 |
| 2004 | 17 | 15 |
| 2005 | 8 | 21 |
| 2006 | 18 | 14 |
| 2007 | 15 | 23 |
| 2008 | 11 | 29 |
| 2009 | 30 | 41 |
| 2010 | 29 | 47 |
| 2011 | 49 | 18 |
| 2012 | 27 | 24 |
| 2013 | 28 | 41 |
| 2014 | 37 | 32 |
| 2015 | 40 | 52 |
| 2016 | 42 | 34 |
| 2017 | 64 | 51 |
| 2018 | 53 | 51 |
| 2019 | 51 | 72 |
| 2020 | 64 | 39 |
| 2021 | 40 | 33 |
| 2022 | 41 | 55 |
| 2023 | 41 | 53 |
| 2024 | 48 | 31 |
| 2025 | 33 | 30 |
| 2026 | 21 | 18 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Processing-in-memory (PIM) device for performing a burst multiplication and accumulation (MAC) operation1 Sep 2026US 12,725,644 B2SK hynix Inc.
- Memory and operating method thereof14 Jul 2026US 12,681,846 B2Gigadevice Semiconductor Inc.
- Semiconductor device23 Jun 2026US 12,664,047 B2Renesas Electronics Corporation
- Reduced pin count stackable memory16 Jun 2026US 12,657,121 B1Raytheon Company
- Apparatuses and methods for input buffer power savings16 Jun 2026US 12,658,243 B2Micron Technology, Inc.
- Memory module with double data rate command and data interfaces supporting two-channel and four-channel modes20 Aug 2026US 2026/0244365 A1Rambus Inc.
- Read operations for a memory array and register13 Aug 2026US 2026/0237411 A1Micron Technology, Inc.
- Dram interface mode with improved channel integrity and efficiency at high signaling rates23 Jul 2026US 2026/0212901 A1Rambus Inc.
- Storage device, system-on-chip including the storage device, and computing apparatus25 Jun 2026US 2026/0178101 A1Shenzhen Microbt Electronics Technology Co., Ltd.
- Reduced pin count stackable memory18 Jun 2026US 2026/0169906 A1Raytheon Company
Most cited
By later US patents
- Memory device supporting a dynamically configurable core organization220US 6,889,304 B2Rambus Inc. · 2005
- Auto-activate on synchronous dynamic random access memory162US 5,600,605 AMicron Technology, Inc. · 1997
- Synchronous DRAM memory with asynchronous column decode136US 5,666,321 AMicron Technology, Inc. · 1997
- Feedback system for accomodating different memory module loading134US 6,745,275 B2VIA Technologies, Inc. · 2004
- Clock vernier adjustment102US 6,115,318 AMicron Technology, Inc. · 2000