Memory module with double data rate command and data interfaces supporting two-channel and four-channel modes
AssigneeRambus Inc.
InventorsDongyun Lee, Steven C. Woo
Life of this patent
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Abstract
A memory module supports multiple memory channel modes, each including a double-date-rate (DDR) data channel supported by an independent command-and-address (CA) channel. In a two-channel mode, the memory module supports two DDR data channels using two respective DDR CA channels. Each CA channel includes a corresponding set of CA links. In a four-channel mode, the memory module supports two pairs of DDR data channels, each pair supported by a pair of independent CA channels. Memory commands issued in the four-channel mode are time interleaved to share one of the sets of CA links.
Claims1
An integrated circuit (IC) buffer component for buffering memory command and address
- (CA) signals, the IC buffer component comprising:
- a first primary CA port to receive a first double-data-rate (DDR) primary CA signal;
- a first demultiplexing circuit to separate the first DDR primary CA signal into first and second single-data-rate (SDR) CA signals;
- first and second secondary CA ports to issue the respective first and second SDR CA signals;
- a second primary CA port to receive a second double-data-rate (DDR) primary CA signal;
- a second demultiplexing circuit to separate the second DDR primary CA signal into third and second single-data-rate (SDR) CA signals;
- and
- third and fourth secondary CA ports to issue the respective third and fourth SDR CA signals.
Dependencies are inferred from the claim text.