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US 12,664,047 B2Granted
Semiconductor device
AssigneeRenesas Electronics Corporation
InventorDaiki Kitagata
Life of this patent
Estimating the term…
Abstract
A semiconductor device includes a semiconductor chip in which a plurality of circuit blocks is formed. The plurality of circuit blocks includes a plurality of logic circuits. Each of the plurality of logic circuits includes an inverter circuit. The inverter circuit outputs a signal according to the result of a logical operation of a first signal and a second signal after being precharged by a trigger signal.
Claims16
A semiconductor device comprising:
- a semiconductor chip formed with a plurality of circuit blocks,
- wherein the plurality of circuit blocks include
- a memory;
- a first input circuit for outputting a signal;
- a first processing circuit including a plurality of logic circuits and processing the signal from the first input circuit;
- and
- a first output circuit for supplying an output of the first processing circuit to the memory,
- wherein each of the plurality of logic circuits includes
- a first N-type MOS transistor having a first terminal, a second terminal, and a first gate terminal for controlling conduction between the first terminal and the second terminal, a first signal from the first input circuit is supplied to the first terminal, and a second signal from the first input circuit is supplied to the first gate terminal;
- a second N-type MOS transistor having a third terminal, a fourth terminal, and a second gate terminal for controlling conduction between the third terminal and the fourth terminal, the second signal is supplied to the third terminal, and the first signal is supplied to the second gate terminal;
- an output driver having an input terminal connected to the second terminal of the first N-type MOS transistor and the fourth terminal of the second N-type MOS transistor;
- and
- a first P-type MOS transistor connected between the input terminal of the output driver and a predetermined voltage, precharging the input terminal of the output driver with a voltage based on the predetermined voltage in response to a first trigger signal supplied to the gate terminal,
- wherein the output driver of the logic circuit outputs a signal according to a result of a logical operation of the first and second signals after being precharged by the first trigger signal.
11 more elements
A semiconductor device comprising:
- a semiconductor chip formed with a plurality of circuit blocks,
- wherein the plurality of circuit blocks include
- a memory;
- an input circuit to which signals are supplied from the memory;
- a plurality of logic circuits;
- a processing circuit that processes signals from the input circuit;
- and
- an output circuit to which signals from the processing circuit are supplied,
- wherein each of the plurality of logic circuits includes
- a first N-type MOS transistor having a first terminal, a second terminal, and a first gate terminal for controlling conduction between the first terminal and the second terminal, a first signal from the input circuit is supplied to the first terminal, and a second signal from the input circuit is supplied to the first gate terminal;
- a second N-type MOS transistor having a third terminal, a fourth terminal, and a second gate terminal that controls conduction between the third terminal and the fourth terminal, the second signal is supplied to the third terminal, and the first signal is supplied to the second gate terminal;
- an output driver having an input terminal connected to the second terminal of the first N-type MOS transistor and the fourth terminal of the second N-type MOS transistor;
- and
- a P-type MOS transistor connected between the input terminal of the output driver and a predetermined voltage, and precharging the input terminal of the output driver with a voltage based on the predetermined voltage in response to a trigger signal supplied to the gate terminal,
- wherein the output driver of the logic circuit outputs a signal according to a result of a logical operation of the first signal and the second signal after being precharged by the trigger signal.
12 more elements
A semiconductor device comprising:
- a pre-stage circuit for generating signals to be written into a memory;
- a processing circuit for processing signals generated by the pre-stage circuit;
- and
- a memory into which signals generated by the processing circuit and signals generated by the pre-stage circuit are written,
- wherein the processing circuit comprises:
- multiple first logic circuits to which signals generated by the pre-stage circuit are supplied;
- and
- multiple second logic circuits to which signals from the multiple first logic circuits are supplied,
- wherein each of the multiple first logic circuits includes
- a first MOS transistor having a first terminal, a second terminal, and a first gate terminal for controlling conduction between the first terminal and the second terminal, and during a processing period, a first signal from the pre-stage circuit is supplied to the first terminal and a second signal from the pre-stage circuit is supplied to the first gate terminal;
- a second MOS transistor having a third terminal, a fourth terminal, and a second gate terminal for controlling conduction between the third terminal and the fourth terminal, and during the processing period, the second signal is supplied to the third terminal and the first signal is supplied to the second gate terminal;
- a first output driver having an input terminal connected to the second terminal of the first MOS transistor and the fourth terminal of the second MOS transistor;
- and
- a third MOS transistor connected between the input terminal of the first output driver and a predetermined first voltage, and precharges the input terminal of the first output driver with a voltage based on the predetermined first voltage during a precharge period before the processing period,
- wherein each of the multiple second logic circuits includes
- fourth MOS transistor having a fifth terminal, a sixth terminal, and a third gate terminal for controlling conduction between the fifth terminal and the sixth terminal, the fifth terminal is connected to an output terminal of an output driver of one of the multiple first logic circuits, and the third gate terminal is connected to an output terminal of an output driver of another of the multiple first logic circuits;
- a fifth MOS transistor having a seventh terminal, an eighth terminal, and a fourth gate terminal for controlling conduction between the seventh terminal and the eighth terminal, the seventh terminal is connected to an output terminal of the other first logic circuit's output driver, and the fourth gate terminal is connected to an output terminal of the one first logic circuit's output driver;
- a second output driver having an input terminal connected to the sixth terminal of the fourth MOS transistor and the eighth terminal of the fifth MOS transistor;
- and
- a sixth MOS transistor connected between the input terminal of the second output driver and the predetermined first voltage, and precharges the input terminal of the second output driver with a voltage based on the predetermined first voltage during the precharge period.
17 more elements
Dependencies are inferred from the claim text.