Apparatuses and methods for input buffer power savings
AssigneeMicron Technology, Inc.
InventorsAkira Yamashita, Kenji Asaki
Life of this patent
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Abstract
Apparatuses and methods for saving power at an input buffer are described. An example apparatus includes an input buffer comprising an amplifier coupled to a pair of serially coupled inverters, and a de-emphasis circuit coupled to the input buffer in parallel with one of the pair of serially-coupled inverters. The de-emphasis circuit comprising a plurality of transistors coupled in parallel to a resistance. The example apparatus further includes an input buffer control circuit configured to selectively enable one of the plurality of transistors to adjust a gain across the one of the pair of inverters based on a latency setting.
Claims20
An apparatus comprising:
- an amplifier coupled to a first terminal and configured to operate at a power based on a first buffer enable signal and a second buffer enable signal and provide an output signal having a gain;
- a de-emphasis circuit coupled in series with a resistor, the de-emphasis circuit configured to selectively adjust the gain based on a latency setting;
- a first logic circuit configured to receive the output signal from the amplifier and provide a second output signal;
- and
- a second logic circuit configured to receive the second output signal from the first logic circuit and an adjusted output signal from the resistor, wherein the second logic circuit is further configured to produce an amplified output signal.
A method comprising:
- selectively enabling first and second transistors of a de-emphasis circuit based on first and second buffer weaken signals;
- and
- adjusting a resistance across the de-emphasis circuit using the first and second transistors to set a gain of an input buffer coupled to the de-emphasis circuit to provide an adjusted output signal.
An apparatus comprising:
- a first transistor configured to receive a first buffer weaken signal and a first signal;
- a second transistor configured to receive a second buffer weaken signal and the first signal;
- and
- a plurality of serially coupled transistors configured to receive a supply voltage and the first signal,
- wherein the first and second transistors are selectively enabled to adjust a gain of the first signal based on a latency setting, and
- wherein the first and second transistors and the plurality of serially coupled transistor are configured to provide an adjusted output signal.
Dependencies are inferred from the claim text.