Auto-activate on synchronous dynamic random access memory

A method of pipelining commands in a memory device having a memory array of storage cells organized in rows and columns for storing data and responsive to command signals, the memory device operating in synchronization with active edges of a system clock, the method comprising the steps of:

• initiating, at a first active edge of the system clock, a first command controlling a first operation on the memory array;
• initiating at a second active edge of the system clock, a second command controlling a second operation on the memory array, wherein the second active edge of the system clock occurs during the first operation;
• indicating when the first operation is completed in response to the first command;
• performing a first portion of the second operation in response to the second command;
• and
• performing a second portion of the second operation in response to the indicating step indicating that the first operation is completed.

A method of performing a transfer operation in a synchronous dynamic random access memory (SDRAM) responsive to command signals and address bits and including a memory array of storage cells organized in rows and columns for storing data, the method comprising the steps of:

• initiating, at different times, a precharge command, an active command, and a transfer command, wherein the active command initiates during the precharge command;
• deactivating and precharging the memory array in response to the precharge command;
• indicating a completion of a precharge command operation;
• receiving and holding a value representing a row address of the memory array as indicated by the address bits provided at the time the active command is initiated;
• releasing the row address and activating a row of storage cells in the memory array in response to the indicating step indicating the completion of the precharge command operation;
• receiving and holding a value representing a column address of the memory array as indicated by the address bits provided at the time the transfer command is initiated;
• and
• transferring data from or to a storage cell of the memory array identified by the released row address and the held column address.