Memory and operating method thereof
AssigneeGigadevice Semiconductor Inc.
InventorsSibo Ma, Hong Hu, Yang Li, Jianzhong Zhao
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AssigneeGigadevice Semiconductor Inc.
InventorsSibo Ma, Hong Hu, Yang Li, Jianzhong Zhao
Estimating the term…
Disclosed are a memory and operation method thereof. The memory comprises a memory array and an access interface for external access to the memory array, the access interface comprising at least one data/address multiplexing line. The method comprises: starting a specified fixed-number-random-access mode, in which the memory array can be continuously read or written in response to receiving a fixed number of random access addresses; sequentially receiving the preset fixed number of access addresses via the data/address multiplexing line in succession; sequentially outputting data read in response to the received access addresses in succession via the data/address multiplexing line in the case where the mode indicates read operations, or sequentially receiving data to be written in response to the received access addresses in succession via the data/address multiplexing line in the case where the mode indicates write operations; and ending the mode by receiving an invalid chip enable signal.
A method for operating a memory, the memory comprising a memory array and an access interface for external access to the memory array, the access interface comprising at least one data/address multiplexing line for transmitting data and address,
Dependencies are inferred from the claim text.