G11C 7/1093
Input synchronization
Official title: {Input synchronization}
G11C7/1093 (Input synchronization) appears on 1,728 US grants and 1,656 published applications in this corpus.
Search patents in G11C- Granted patents
- 1,728
- Published applications
- 1,656
- Assignees
- 221
- Inventors
- 1,960
- Latest grant
- 22 Sep 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1983 | 1 | 0 |
| 1984 | 1 | 0 |
| 1985 | 0 | 0 |
| 1986 | 0 | 0 |
| 1987 | 1 | 0 |
| 1988 | 3 | 0 |
| 1989 | 4 | 0 |
| 1990 | 6 | 0 |
| 1991 | 2 | 0 |
| 1992 | 0 | 0 |
| 1993 | 4 | 0 |
| 1994 | 9 | 0 |
| 1995 | 3 | 0 |
| 1996 | 6 | 0 |
| 1997 | 2 | 0 |
| 1998 | 15 | 0 |
| 1999 | 11 | 0 |
| 2000 | 10 | 0 |
| 2001 | 24 | 8 |
| 2002 | 14 | 13 |
| 2003 | 13 | 19 |
| 2004 | 16 | 25 |
| 2005 | 21 | 53 |
| 2006 | 43 | 39 |
| 2007 | 36 | 50 |
| 2008 | 48 | 28 |
| 2009 | 32 | 52 |
| 2010 | 50 | 44 |
| 2011 | 46 | 41 |
| 2012 | 35 | 48 |
| 2013 | 50 | 49 |
| 2014 | 53 | 47 |
| 2015 | 62 | 74 |
| 2016 | 92 | 61 |
| 2017 | 82 | 64 |
| 2018 | 64 | 73 |
| 2019 | 112 | 124 |
| 2020 | 126 | 109 |
| 2021 | 127 | 113 |
| 2022 | 96 | 121 |
| 2023 | 119 | 151 |
| 2024 | 121 | 121 |
| 2025 | 122 | 79 |
| 2026 | 46 | 50 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Signal retiming within memory systems22 Sep 2026US 12,744,065 B2Micron Technology, Inc.
- Interface circuit for converting a serial data stream to a parallel data scheme with data strobe preamble information in the serial data stream15 Sep 2026US 12,737,139 B2Rambus Inc.
- Memory system25 Aug 2026US 12,717,690 B2SK hynix Inc.
- Memory system and memory chip25 Aug 2026US 12,717,732 B2Etron Technology, Inc.
- Apparatuses, systems, and methods for data timing alignment with fast alignment mode25 Aug 2026US 12,718,866 B2Micron Technology, Inc.
- Semiconductor apparatus adjusting a phase skew between a clock signal and data24 Sep 2026US 2026/0290417 A1SK hynix Inc.
- Controller configured to control memory device, operation method of controller, and storage device including memory device and controller17 Sep 2026US 2026/0279419 A1Samsung Electronics Co., Ltd.
- Read operations for a memory array and register13 Aug 2026US 2026/0237411 A1Micron Technology, Inc.
- Pulse based multi-level cell programming6 Aug 2026US 2026/0229261 A1Micron Technology, Inc.
- Low-latency word alignment for serdes interfaces using inline patterns30 Jul 2026US 2026/0219701 A1QUALCOMM Incorporated
Most cited
By later US patents
- Low skew differential receiver with disable feature220US 6,256,234 B1Micron Technology, Inc. · 2001
- Memory device with staggered data paths213US 5,831,929 AMicron Technology, Inc. · 1998
- Internal clock generating circuit for clock synchronous semiconductor memory device203US 6,636,110 B1Mitsubishi Denki Kabushiki Kaisha · 2003
- Method and apparatus for determining actual write latency and accurately aligning the start of data capture with the arrival of data at a memory device164US 6,697,926 B2Micron Technology, Inc. · 2004
- Line buffer type semiconductor memory device capable of direct prefetch and restore operations159US 6,347,055 B1NEC Corporation · 2002