Internal clock generating circuit for clock synchronous semiconductor memory device

A semiconductor circuit device, comprising:

• clock generating circuitry for generating a clock signal;
• a plurality of internal circuits each operating in accordance with an applied clock signal, said plurality of internal circuits being arranged in a region between a first node of a minimum delay physically nearest to said clock generating circuitry and a second node of maximum delay physically farthest from said clock generating circuitry;
• and
• a clock distributing circuit including (i) a plurality of nodes arranged in a form of a tree with a node corresponding to a middle point between the first and second nodes being a starring node, each node connected to clock transmission lines extending in mutually opposite directions and (ii) clock drivers arranged corresponding to respective nodes for transmitting an applied clock signals to corresponding clock transmission lines, for transmitting the clock signal from said clock generating circuitry to said plurality of internal circuits, wherein said clock generating circuitry includes:
• a clock buffer circuit for receiving an externally applied external clock signal to produce a first internal clock signal according to the external clock signal;
• a phase comparator for comparing in phase the first internal clock signal and a feedback clock signal fed back from the clock distributing circuit;
• a delay stage for delaying a received clock for outputting;
• a delay control circuit according to an output signal of said phase comparator for adjusting a delay amount of said delay stage such that a phase difference between the first internal clock signal and the feedback clock signal becomes substantially zero;
• a frequency divider for receiving a middle signal having a delay amount of half a whole delay amount of said delay stage from said delay stage to frequency-divide the middle signal by a predetermined factor,
• a first selector responsive to a first selecting signal for selecting one of said first internal clock signal and said middle signal for application to said delay stage;
• and
• a first selecting circuit responsive to an operation mode designating signal for selecting one of an output signal of said frequency-divider and an output of said delay stage to generate a second internal clock signal as said clock signal.

A semiconductor device comprising:

• an internal clock generating circuitry for generating an internal clock signal in accordance with an external clock signal;
• a clock tree arranged on a common semiconductor substrate on the internal clock generating circuitry and including a plurality of nodes for distributing the internal clock signal from a starting point to terminal points;
• an internal control signal generator provided corresponding to a terminal point of said plurality of terminal points and responsive to a clock signal at the terminal point for generating an internal control signal for controlling an internal operation;
• said internal clock generating circuitry receiving a clock signal at a predetermined terminal point of the terminal points to adjust a phase difference between the external clock signal and the received clock signal for generating said internal clock signal.

A semiconductor memory device comprising:

• signal input circuitry for receiving an input signal and generating an internal signal;
• latch circuitry for receiving and latching said internal signal;
• and
• control signal generating circuitry for generating an input control signal controlling taking in of said input signal by said input circuitry and a latch control signal controlling latching operation of said latch circuitry in accordance with a basic signal, said control signal generating circuitry including an adjusting circuit for compensating for a time difference between taking in of said input signal by said input circuitry and latching of said internal signal by said latch circuitry,
• wherein said adjusting circuit comprises delay circuitry for delaying said input control signal, by a time period corresponding to a signal propagation time of said internal signal from said input circuitry to said latch circuitry, to generate said latch control signal.

A semiconductor memory device comprising:

• signal input circuitry for receiving an input signal and generating an internal signal;
• latch circuitry for receiving and latching said internal signal;
• and
• control signal generating circuitry for generating an input control signal controlling taking in of said input signal by said input circuitry and a latch control signal controlling latching operation of said latch circuitry in accordance with a basic signal, said control signal generating circuitry including an adjusting circuit for compensating for a time difference between taking in of said input signal by said input circuitry and latching of said internal signal by said latch circuitry,
• wherein said adjusting circuitry comprises a delay circuit for adjusting a phase difference between said input control signal and said latch control signal.

A semiconductor device comprising:

• adjusting circuitry for adjusting a phase difference between an external clock signal applied to an external clock input node and a feed back internal clock signal at a feed back clock node fed back from a predetermined internal clock mode receiving an internal clock signal, and generating a reference internal clock signal and a pro-external clock signal;
• and
• internal clock generating circuitry for generating said internal clock signal synchronized with said external clock signal in accordance with said reference clock signal and said pro-external clock signal;
• said adjusting circuitry adjusting said phase difference such that a propagation delay of the external clock signal between the external clock input node and an input of said internal clock generating circuitry is made equal to a propagation delay of the feed back clock signal between the predetermined internal clock node and the input of the internal clock generating circuitry.