Pulse based multi-level cell programming
AssigneeMicron Technology, Inc.
InventorsHernan A. Castro, Mattia Boniardi, Innocenzo Tortorelli
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AssigneeMicron Technology, Inc.
InventorsHernan A. Castro, Mattia Boniardi, Innocenzo Tortorelli
Estimating the term…
Methods, systems, and devices for pulse based multi-level cell programming are described. A memory device may identify an intermediate logic state to store to a multi-level memory cell capable of storing three or more logic states. The memory device may apply a first pulse with a first polarity to the memory cell to store a SET or RESET state to the memory cell based on identifying the intermediate logic state. As such, the memory device may identify a threshold voltage of the memory cell that stores the SET or RESET state. The memory device may apply a quantity of pulses to the memory cell to store the identified intermediate logic state based on identifying the threshold voltage of the memory cell that stores the SET or RESET state. In some examples, the quantity of pulses may have a second polarity different than the first polarity.
A memory system, comprising:
A non-transitory computer-readable medium storing code, the code comprising instructions executable by one or more processors of a memory system to:
A method, comprising:
Dependencies are inferred from the claim text.