G11C 2216/14
Circuits or methods to write a page or sector of information simultaneously
Official title: Circuits or methods to write a page or sector of information simultaneously into a nonvolatile memory, typically a complete row or word line in flash memory
G11C2216/14 (Circuits or methods to write a page or sector of information simultaneously) appears on 402 US grants and 394 published applications in this corpus.
Search patents in G11C- Granted patents
- 402
- Published applications
- 394
- Assignees
- 93
- Inventors
- 528
- Latest grant
- 9 Sep 2025
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1978 | 1 | 0 |
| 1979 | 0 | 0 |
| 1980 | 0 | 0 |
| 1981 | 0 | 0 |
| 1982 | 0 | 0 |
| 1983 | 0 | 0 |
| 1984 | 0 | 0 |
| 1985 | 0 | 0 |
| 1986 | 0 | 0 |
| 1987 | 1 | 0 |
| 1988 | 1 | 0 |
| 1989 | 0 | 0 |
| 1990 | 3 | 0 |
| 1991 | 2 | 0 |
| 1992 | 1 | 0 |
| 1993 | 0 | 0 |
| 1994 | 3 | 0 |
| 1995 | 0 | 0 |
| 1996 | 2 | 0 |
| 1997 | 1 | 0 |
| 1998 | 2 | 0 |
| 1999 | 1 | 0 |
| 2000 | 3 | 0 |
| 2001 | 1 | 2 |
| 2002 | 6 | 6 |
| 2003 | 5 | 15 |
| 2004 | 15 | 13 |
| 2005 | 14 | 19 |
| 2006 | 21 | 39 |
| 2007 | 26 | 47 |
| 2008 | 35 | 34 |
| 2009 | 31 | 37 |
| 2010 | 32 | 28 |
| 2011 | 28 | 20 |
| 2012 | 33 | 29 |
| 2013 | 24 | 15 |
| 2014 | 22 | 13 |
| 2015 | 10 | 5 |
| 2016 | 6 | 4 |
| 2017 | 12 | 8 |
| 2018 | 6 | 11 |
| 2019 | 11 | 15 |
| 2020 | 17 | 13 |
| 2021 | 11 | 9 |
| 2022 | 8 | 4 |
| 2023 | 3 | 0 |
| 2024 | 2 | 4 |
| 2025 | 2 | 3 |
| 2026 | 0 | 1 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Dual address encoding for logical-to-physical mapping9 Sep 2025US 12,411,775 B2
- Configurable types of write operations18 Feb 2025US 12,230,232 B2Micron Technology, Inc.
- Storage device and method of operating the storage device8 Oct 2024US 12,112,799 B2SK hynix Inc.
- Dual address encoding for logical-to-physical mapping11 Jun 2024US 12,007,903 B2
- Nonvolatile memory device including a fast read page and a storage device including the same1 Aug 2023US 11,715,516 B2Samsung Electronics Co., Ltd.
- Memory device and operation method therof16 Apr 2026US 2026/0105967 A1Macronix International Co., Ltd.
- Dual address encoding for logical-to-physical mapping25 Dec 2025US 2025/0390436 A1Lodestar Licensing Group LLC
- Dynamic latches above a three-dimensional non-volatile memory array20 Nov 2025US 2025/0356922 A1Micron Technology, Inc.
- Configurable types of write operations17 Jul 2025US 2025/0232744 A1Micron Technology, Inc.
- Storage device and method of operating the storage device5 Dec 2024US 2024/0404589 A1SK hynix Inc.
Most cited
By later US patents
- Programming method to reduce gate coupling interference for non-volatile memory460US 7,400,532 B2Micron Technology, Inc. · 2008
- Operation of a non-volatile memory array458US 7,924,628 B2Spansion Israel Ltd · 2011
- Flash eeprom system with simultaneous multiple data sector programming and storage of physical block characteristics in other designated blocks412US 6,426,893 B1SanDisk Corporation · 2002
- Nonvolatile semiconductor memory having plural data storage portions for a bit line connected to memory cells274US 6,373,746 B1Kabushiki Kaisha Toshiba · 2002
- Multiple bits per-cell flash EEPROM capable of concurrently programming and verifying memory cells and reference cells221US 5,712,815 AAdvanced Micro Devices, Inc. · 1998