Operation of a non-volatile memory array
AssigneeSpansion Israel Ltd
InventorsKobi Danon, Shai Eisen, Marcelo Krygier
Life of this patent
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Abstract
A cache programming operation which requires 2 SRAMs (one for the user and one for the array) may be combined with a multi-level cell (MLC) programming operation which also requires 2 SRAMs (one for caching the data and one for verifying the data), using only a total of two SRAMs (or buffers). One of the buffers (User SRAM) receives and stores user data. The other of the two buffers (Cache SRAM) may perform a caching function as well as a verify function. In this manner, if a program operation fails, the user can have its original data back so that he can try to reprogram it to a different place (address).
Claims17
A non-volatile memory (“NVM”) device comprising a first buffer adapted to receive data from an interface;
- a second buffer adapted to receive data derived from data in said first buffer;
- and
- control logic adapted to program an NVM array using data in said second buffer, wherein programming of the NVM array includes modifying data in said second buffer during a first phase of programming and refreshing data in said second buffer with at least some data from said first buffer prior to a second phase of programming.
A method of programming a non-volatile memory (“NVM”) device comprising:
- placing data in a first buffer;
- placing data in a second buffer derived from data in the first buffer;
- and
- programming an NVM array using data in said second buffer, wherein programming of the NVM array includes modifying data in said second buffer during a first phase of programming and refreshing data in said second buffer with at least some data from said first buffer prior to a second phase of programming.
Dependencies are inferred from the claim text.