Memory device and operation method therof
AssigneeMacronix International Co., Ltd.
InventorsWei-Han Chen, E-Yuan Chang, Yih-Shan Yang
Life of this patent
Estimating the term…
Abstract
A memory device may be a 3D NAND flash memory circuit, and provides a high-capacity storage medium with favorable performance. The memory device includes a plurality of page buffers and a plurality of first switches. The page buffers are coupled in series. The first switches respectively correspond to the page buffers, wherein each of the first switches is coupled to a sensing node of corresponding page buffer. Each of the first switches receives a reference voltage and provides a source current to the sensing node of corresponding page buffer after a data sensing period.
Claims19
A memory device, comprising:
- a plurality of page buffers, wherein the plurality of page buffers are coupled in series;
- and
- a plurality of first switches, respectively corresponding to the plurality of page buffers, wherein each of the plurality of first switches is coupled to a sensing node of the corresponding page buffer,
- wherein each of the plurality of first switches receives a reference voltage, and provides a source current to the sensing node of the corresponding page buffer after a data sensing period.
An operation method of a memory device, comprising:
- providing a plurality of page buffers coupled in series;
- configuring a plurality of first switches to respectively correspond to the plurality of page buffers, such that each of the plurality of first switches is coupled to a sensing node of the corresponding page buffer;
- and
- enabling each of the plurality of first switches to provide a source current to the sensing node of the corresponding page buffer according to a received reference voltage after a data sensing period.
Dependencies are inferred from the claim text.