Dynamic latches above a three-dimensional non-volatile memory array

A memory device comprising:

• a substrate;
• a page buffer circuit disposed above the substrate;
• a memory array disposed above the page buffer circuit, the memory array comprising a plurality of block groups, each block group comprising a plurality of blocks, and each block comprising a plurality of sub-blocks;
• and
• a logic layer disposed above the memory array, the logic layer disposed above the memory array comprising a plurality of latches to store a multi-bit data pattern representing a sequence of bits to be programmed to respective memory cells of the plurality of sub-blocks of one of the plurality of blocks of the memory array.

A memory device comprising:

• a substrate;
• a page buffer circuit disposed above the substrate;
• a memory array disposed above the page buffer circuit, the memory array comprising a plurality of block groups, each block group comprising a plurality of blocks, and each block comprising a plurality of sub-blocks;
• and
• a logic layer disposed above the memory array, the logic layer disposed above the memory array comprising a plurality of latches to store a multi-bit data pattern representing a sequence of bits to be programmed to respective memory cells of the plurality of sub-blocks of one of the plurality of blocks of the memory array;
• and
• control logic coupled to the memory array and to the logic layer disposed above the memory array.