G06F 9/38875
For adaptable or variable architectural vector length
Official title: {for adaptable or variable architectural vector length}
G06F9/38875 (For adaptable or variable architectural vector length) appears on 11 US grants and 18 published applications in this corpus.
Search patents in G06F- Granted patents
- 11
- Published applications
- 18
- Assignees
- 10
- Inventors
- 42
- Latest grant
- 17 Feb 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 2000 | 1 | 0 |
| 2001 | 0 | 0 |
| 2002 | 0 | 0 |
| 2003 | 0 | 0 |
| 2004 | 0 | 0 |
| 2005 | 0 | 0 |
| 2006 | 0 | 0 |
| 2007 | 0 | 0 |
| 2008 | 0 | 0 |
| 2009 | 0 | 0 |
| 2010 | 0 | 0 |
| 2011 | 0 | 2 |
| 2012 | 0 | 3 |
| 2013 | 0 | 0 |
| 2014 | 1 | 3 |
| 2015 | 4 | 0 |
| 2016 | 0 | 0 |
| 2017 | 2 | 1 |
| 2018 | 1 | 0 |
| 2019 | 0 | 0 |
| 2020 | 0 | 0 |
| 2021 | 0 | 1 |
| 2022 | 0 | 0 |
| 2023 | 0 | 2 |
| 2024 | 1 | 2 |
| 2025 | 0 | 2 |
| 2026 | 1 | 2 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Implementing specialized floating point instructions on an integer pipeline for accelerating dynamic programming algorithms17 Feb 2026US 12,554,493 B2NVIDIA Corporation
- Implementing specialized instructions for accelerating dynamic programming algorithms12 Nov 2024US 12,141,582 B2NVIDIA Corporation
- Apparatus and method for transferring a plurality of data structures between memory and a plurality of vector registers23 Jan 2018US 9,875,214 B2Apple Inc.
- Processor architecture and method for simplifying programming single instruction, multiple data within a register31 Jan 2017US 9,557,993 B2Analog Devices Global
- Integrated circuit with control node circuitry and processing circuitry24 Jan 2017US 9,552,206 B2Texas Instruments Incorporated
- Implementing specialized floating point instructions on an integer pipeline for accelerating dynamic programming algorithms5 Mar 2026US 2026/0064415 A1NVIDIA Corporation
- Memory latency aware tiling for generalized matrix multiplications on parallel processors1 Jan 2026US 2026/0003932 A1Advanced Micro Devices, Inc.
- Sub-vector-supporting instruction for scalable vector instruction set architecture15 May 2025US 2025/0156184 A1Arm Limited
- Implementing specialized instructions for accelerating dynamic programming algorithms27 Feb 2025US 2025/0068421 A1NVIDIA Corporation
- Vector processor performing vector and element reduction method with same circuit structure25 Jul 2024US 2024/0248713 A1Andes Technology Corporation
Most cited
By later US patents
- DPS having a plurality of like processors controlled in parallel by an instruction word, and a control processor also controlled by the instruction word70US 6,088,783 A2000
- Processor architecture and method for simplifying programming single instruction, multiple data within a register13US 9,557,993 B2Analog Devices Global · 2017
- Integrated circuit with control node circuitry and processing circuitry11US 9,552,206 B2Texas Instruments Incorporated · 2017
- Predicting a result for an actual instruction when processing vector instructions5US 9,098,295 B2Apple Inc. · 2015
- Apparatus and method for transferring a plurality of data structures between memory and a plurality of vector registers2US 9,875,214 B2Apple Inc. · 2018