Predicting a result for an actual instruction when processing vector instructions

A processor that executes vector instructions, comprising:

• an execution unit in the processor;
• and
• a dispatch unit in the processor;
• wherein, while dispatching instructions at runtime, upon encountering an Actual instruction, the dispatch unit is configured to determine if a result of the Actual instruction is predictable;
• upon determining that the result of the Actual instruction is predictable, the dispatch unit is configured to dispatch a prediction micro-operation associated with the Actual instruction, wherein the prediction micro-operation generates a predicted result vector for the Actual instruction;
• and
• wherein the execution unit is configured to execute the prediction micro-operation, which comprises:
• optionally receiving a predicate vector;
• generating a predicted result vector, wherein, if the predicate vector is received, for each element of the predicted result vector for which the predicate vector is active, otherwise, for each element of the predicted result vector, generating the predicted result vector comprises setting the element of the predicted result vector to true.

A computer system that executes vector instructions, comprising:

• a processor;
• a memory coupled to the processor, wherein the memory is configured to store data and instructions for the processor;
• an execution unit in the processor;
• and
• a dispatch unit in the processor;
• wherein, while dispatching instructions at runtime, upon encountering an Actual instruction, the dispatch unit is configured to determine if a result of the Actual instruction is predictable;
• upon determining that the result of the Actual instruction is predictable, the dispatch unit is configured to dispatch a prediction micro-operation associated with the Actual instruction, wherein the prediction micro-operation generates a predicted result vector for the Actual instruction;
• and
• wherein the execution unit is configured to execute the prediction micro-operation, which comprises:
• optionally receiving a predicate vector;
• generating a predicted result vector, wherein, if the predicate vector is received, for each element of the predicted result vector for which the predicate vector is active, otherwise, for each element of the predicted result vector, generating the predicted result vector comprises setting the element of the predicted result vector to true.

A method for executing a vector instruction in a processor, comprising:

• while dispatching instructions at runtime, encountering an Actual instruction and receiving a predicate vector for the Actual instruction;
• upon determining that a result of the Actual instruction is predictable, using the predicate vector as a predicted result vector for the Actual instruction;
• and
• before dispatching subsequent vector instructions that depend on the Actual instruction for execution, modifying the dependency of the subsequent vector instructions from an actual result vector from the Actual instruction to the predicted result vector so that the predicted result vector is used to execute the subsequent vector instructions instead of the actual result vector.

A processor for executing a vector instruction, comprising:

• an execution unit in the processor;
• and
• a dispatch unit in the processor;
• wherein, while dispatching instructions at runtime, upon encountering an Actual instruction and receiving a predicate vector for the Actual instruction, the dispatch unit is configured to determine if a result of the Actual instruction is predictable;
• upon determining that a result of the Actual instruction is predictable, the dispatch unit is configured to set the predicate vector as a predicted result vector for the Actual instruction;
• and
• before dispatching subsequent vector instructions that depend on the Actual instruction for execution, the dispatch unit is configured to modify the dependency of the subsequent vector instructions from an actual result vector from the Actual instruction to the predicted result vector so that the execution unit uses the predicted result vector to execute the subsequent vector instructions instead of the actual result vector.