Vector processor performing vector and element reduction method with same circuit structure
AssigneeAndes Technology Corporation
InventorChia-Wei Hsu
Life of this patent
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Abstract
A vector processor performing a vector reduction method and an element reduction method with the same circuit structure is provided. The vector processor includes a vector register file and a first lane. The first lane loads a first operand and a second operand based on a first state parameter and performs a first reduction operation on the first operand and the second operand to generate a first reduction result. The first lane performs a second reduction operation on the first and second parts of the first reduction result based on a second state parameter to generate a second reduction result.
Claims9
A vector processor, comprising:
- a vector register file;
- and
- a first lane coupled to the vector register file for loading a first operand and a second operand based on a first state parameter, wherein the first lane performs a first reduction operation on the first operand and the second operand to generate a first reduction result, and the first lane performs a second reduction operation on a first part of the first reduction result and a second part of the first reduction result based on a second state parameter to generate a second reduction result.
An element reduction method, comprising:
- loading a first operand and a second operand based on a first state parameter and performing a first reduction operation on the first operand and the second operand to generate a first reduction result;
- and
- performing a second reduction operation on a first part and a second part of the first reduction result based on a second state parameter to generate a second reduction result.
Dependencies are inferred from the claim text.