G06F 9/3887
Controlled by a single instruction for multiple data lanes [simd]
Official title: {controlled by a single instruction for multiple data lanes [SIMD]}
G06F9/3887 (Controlled by a single instruction for multiple data lanes [simd]) appears on 1,654 US grants and 1,995 published applications in this corpus.
Search patents in G06F- Granted patents
- 1,654
- Published applications
- 1,995
- Assignees
- 283
- Inventors
- 2,604
- Latest grant
- 6 Oct 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1976 | 1 | 0 |
| 1977 | 0 | 0 |
| 1978 | 1 | 0 |
| 1979 | 0 | 0 |
| 1980 | 0 | 0 |
| 1981 | 1 | 0 |
| 1982 | 0 | 0 |
| 1983 | 0 | 0 |
| 1984 | 1 | 0 |
| 1985 | 1 | 0 |
| 1986 | 3 | 0 |
| 1987 | 0 | 0 |
| 1988 | 3 | 0 |
| 1989 | 2 | 0 |
| 1990 | 1 | 0 |
| 1991 | 4 | 0 |
| 1992 | 1 | 0 |
| 1993 | 3 | 0 |
| 1994 | 3 | 0 |
| 1995 | 3 | 0 |
| 1996 | 20 | 0 |
| 1997 | 15 | 0 |
| 1998 | 32 | 0 |
| 1999 | 12 | 0 |
| 2000 | 10 | 0 |
| 2001 | 10 | 4 |
| 2002 | 3 | 7 |
| 2003 | 8 | 5 |
| 2004 | 5 | 24 |
| 2005 | 10 | 21 |
| 2006 | 12 | 19 |
| 2007 | 10 | 25 |
| 2008 | 15 | 37 |
| 2009 | 24 | 28 |
| 2010 | 24 | 34 |
| 2011 | 28 | 49 |
| 2012 | 38 | 39 |
| 2013 | 46 | 53 |
| 2014 | 44 | 74 |
| 2015 | 46 | 98 |
| 2016 | 70 | 107 |
| 2017 | 113 | 96 |
| 2018 | 100 | 167 |
| 2019 | 119 | 134 |
| 2020 | 142 | 113 |
| 2021 | 123 | 143 |
| 2022 | 129 | 139 |
| 2023 | 106 | 138 |
| 2024 | 133 | 130 |
| 2025 | 110 | 115 |
| 2026 | 69 | 196 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Subgroups
Granted patents
Recent patents
- Cache structure and utilization6 Oct 2026US 12,754,876 B2Intel Corporation
- Systems, methods, and apparatuses for heterogeneous computing29 Sep 2026US 12,748,618 B2Intel Corporation
- Efficient selection of single instruction multiple data operations for neural processing units29 Sep 2026US 12,748,723 B2Tesla, Inc.
- Recursive generation and distribution of command bundles at core array22 Sep 2026US 12,743,396 B1OXMIQ Labs Inc.
- Systems and methods for updating memory side caches in a multi-GPU configuration15 Sep 2026US 12,737,317 B2Intel Corporation
- Efficient matrix multiply and add with a group of warps1 Oct 2026US 2026/0299943 A1NVIDIA Corporation
- Encryption compute apparatus and method with compute grid partitioning and reconfiguration1 Oct 2026US 2026/0299960 A1Intel Corporation
- Convolutional neural network operations1 Oct 2026US 2026/0300428 A1Advanced Micro Devices, Inc.
- Chiplet-integrated machine learning accelerators24 Sep 2026US 2026/0288661 A1Advanced Micro Devices, Inc.
- Direct memory access systems24 Sep 2026US 2026/0288675 A1NVIDIA Corporation
Most cited
By later US patents
- Method and system for efficient matrix multiplication in a SIMD processor architecture531US 7,873,812 B12011
- Vector processor system420US 8,356,144 B22013
- Processing array data on SIMD multi-core processor architectures418US 8,484,276 B2International Business Machines Corporation · 2013
- Active memory data compression system and method418US 9,015,390 B2Micron Technology, Inc. · 2015
- Multi-processor reconfigurable in single instruction multiple data (SIMD) and multiple instruction multiple data (MIMD) modes and method of operation402US 5,212,777 ATexas Instruments Incorporated · 1993