Active memory data compression system and method

A computer system, comprising:

• a host processor;
• a peripheral device coupled to the host processor;
• a memory controller coupled to the host processor and the peripheral device;
• and
• an integrated circuit active memory device, comprising:
• a memory device having a data bus containing a plurality of data bus bits;
• an array of processing elements each of which is coupled to a respective group of the data bus bits, each of the processing elements having an instruction input coupled to receive processing element instructions for controlling the operation of the processing elements;
• register files coupled to the array of processing elements and the memory device, the register files transferring data between the processing elements and the memory device;
• a host/memory interface coupled to the memory controller and coupled to the memory device, the host/memory interface being operable to receive direct access memory commands to provide direct access to the memory device to transfer compressed data to or from the peripheral device and the active memory device;
• a task buffer coupled to the memory controller and a command engine, the task buffer operable to receive high level task commands from the memory controller and provide the high level commands to the command engine in an order received, wherein the high level task commands include a task address;
• a command engine coupled to the task buffer, the command engine being operable to receive task commands from the task buffer and operable to generate corresponding sequences of processing element instructions and memory instructions responsive to respective task commands to control the operation of the memory device and the processing elements to generate corresponding sequences of instructions responsive to memory commands to read data from and write data to the memory device, at least some of the instructions generated by the command engine responsive to the task commands causing the processing elements to decompress compressed data transferred to the active memory device through the host interface port and store the decompressed data in the memory device or to compress decompressed data read from the memory device, and to transfer the compressed data from the active memory device through the host interface port;
• a processing element instructions buffer coupled to the command engine and an array control unit, the processing element instructions buffer operable to receive sequences of processing element instructions from the command engine and provide the sequences of processing element instructions to the array control unit in an order received;
• the array control unit coupled to the processing element instructions buffer and the processing elements, the array control unit being operable to receive sequences of processing element instructions from the processing element instructions buffer and to generate array control unit microinstructions responsive to the sequences of processing element instructions received from the processing element instructions buffer, at least some of the microinstructions causing the processing elements to either decompress data transferred from the peripheral literal device to the active memory device through the host interface/memory interface and then store the decompressed data in the memory device or to compress previously decompressed data transferred from the memory device that is to be transferred to the peripheral device through the host/memory interface;
• a memory instructions buffer coupled to the command engine and a memory device control unit, the memory instructions buffer operable to receive sequences of memory instructions from the command engine and provide the sequences of memory instructions to the memory device in an order received;
• and
• the memory device control unit coupled to the memory instructions buffer and the memory device, the memory device control unit operable to receive sequences of memory instructions from the memory instructions buffer and to generate memory commands responsive to the sequences of memory instructions received from memory instructions buffer.

A computer system, comprising:

• a host processor;
• a peripheral device coupled to the host processor;
• a memory controller coupled to the host processor and the peripheral device;
• and
• an integrated circuit active memory device, comprising:
• a task command interface coupled to the memory controller and configured to receive task commands, wherein the task commands include a task address, and wherein the task command interface is a first-in, first-out buffer and provides the task commands in an order received;
• a host/memory interface coupled to the memory controller, the host/memory interface being operable to transfer data to or from the peripheral device and the active memory device;
• a processor operable to decompress compressed data that has been transferred to the active memory device through the host/memory interface and to compress the uncompressed data to be transferred through the host/memory interface from the active memory device;
• a memory device coupled to the processor, the memory device being operable to store uncompressed data and compressed data;
• register files coupled to the processor and the memory device, the register files configured to provide compressed data from the memory device to the processor to be decompressed and further configured to provide uncompressed data from the memory device to the processor to be compressed;
• a task command engine coupled to the task command interface and operable to generate processing instructions for the processor and memory instructions for the memory device responsive to respective task commands including the task address;
• a processing instructions buffer coupled to the task command engine and an array control unit, the processing instruction buffer operable to receive the processing instructions from the task command engine and provide the processing instructions to the array control unit in an order received;
• the array control unit coupled to the task command engine and processor, the array control unit operable to receive the processing instructions from the processing instructions buffer and to generate microinstructions responsive to the processing instructions received from the processing instructions buffer and provide the microinstructions to the processor, at least some of the microinstructions causing the processor to either decompress compressed data transferred from the memory device or to compress uncompressed data transferred from the memory device;
• a memory instructions buffer coupled to the task command engine and a memory device, the memory instructions buffer operable to receive the memory instructions from the task command engine and provide the memory instructions to the memory device in an order received;
• and
• the memory device control unit coupled to the memory instructions buffer and the memory device, the memory device control unit operable to receive memory instructions from the memory instructions buffer and to generate memory commands responsive to the memory instructions received from the memory instructions buffer.