Convolutional neural network operations

An apparatus for executing operations on SIMD units, comprising:

• a SIMD unit comprising a lane and vector general purpose registers (VGPRs) associated with the lane,
• wherein the lane is configured to execute a dot-product instruction during a clock cycle of the lane using operands stored in the VGPRs, the dot-product instruction generating a convolution result for a data element of input data and applying one or more transitional operations to the convolution result to generate an output data element,
• wherein the one or more transitional operations include any one or any combination of a reformatting operation, a rectifying operation, and a clamping operation.

A non-transitory computer-readable medium comprising instructions executable by at least one processor to cause an apparatus to perform operations comprising:

• executing, by a lane of a wave executing on a single-instruction-multiple-data (SIMD) unit, a dot-product instruction during a clock cycle of the lane using operands stored in vector general purpose registers (VGPRs) of the lane, the dot-product instruction generating a convolution result for a data element of input data and applying one or more transitional operations to the convolution result to generate an output data element,
• wherein the one or more transitional operations include any one or any combination of a reformatting operation, a rectifying operation, and a clamping operation.