DPS having a plurality of like processors controlled in parallel by an instruction word, and a control processor also controlled by the instruction word

A method for operating a digital data processor, comprising the steps of:

• composing individual ones of a plurality of instructions and storing the plurality of instructions in a memory that is coupled to a digital data processor, the digital data processor comprising a first processing element and a plurality of second processing elements;
• accessing an instruction from the memory;
• applying the accessed instruction to the digital data processor;
• controlling an operation of the first processing element of the digital data processor with at least one first portion of the accessed instruction;
• and
• simultaneously controlling an operation of the plurality of second processing elements of the digital data processor with at least one second portion of the accessed instruction, said at least one second portion providing identical control to the plurality of second processing elements, wherein an operation specified for the first processing element is calculating a memory address for referencing multiple memory locations whose contents are used or updated by the plurality of second processing elements.

A method for operating a digital data processor, comprising the steps of:

• accessing a first instruction from a memory that is coupled to a digital data processor, the digital data processor comprising a first processing element and a plurality of second processing elements, the first instruction being comprised of a plurality of fields;
• applying the accessed first instruction to the digital data processor;
• controlling an operation of the first processing element of the digital data processor with m first fields of the accessed instruction, where m is a positive integer that is greater than or equal to one;
• and
• simultaneously controlling during the execution of the first instruction an operation of each of the plurality of second processing elements of the digital data processor with n second fields of the accessed instruction, where n is greater than or equal to one, said n second fields providing identical control to the plurality of second processing elements.

A method for operating a digital data processor, comprising steps of:

• providing n functionally identical first processing elements and a second processing element, where n is an integer greater than one, wherein an operation of each of the n first processing elements and an operation of the second processing element are locked together during an execution of a single instruction word;
• during the execution of a first type of instruction word that specifies a first data type for the n first processing elements, accessing data from a plurality of adjacent memory locations as n sets of two byte data elements, an individual one of the n sets being associated with one of the n first processing elements;
• during the execution of a second type of instruction word that specifies a second data type for the n first processing elements, accessing data from a plurality of adjacent memory locations as n sets of one byte data elements, an individual one of the n sets being associated with one of the n first processing elements;
• and
• during the execution of a third type of instruction word that specifies a third data type for the n first processing elements, accessing data from a plurality of non-adjacent memory locations as n sets of data elements, an individual one of the n sets being associated with one of the n first processing elements, and
• further comprising a step of calculating, with the second processing element, an address of the plurality of adjacent or non-adjacent memory locations.