Processor architecture and method for simplifying programming single instruction, multiple data within a register

A method to be performed by a processor, the method comprising:

• issuing an instruction to one or more processing elements which include one or more registers divisible into processing lanes for parallel processing;
• setting each of mask bits corresponding with the processing lanes to a first state or a second state when a loop count of a loop of an operation associated with the instruction indicates that the operation is in a last iteration of the loop and setting all of the mask bits to the first state otherwise;
• enabling processing lanes having corresponding mask bits of the first state to execute the instruction;
• and
• disabling processing lanes having corresponding mask bits of the second state from executing the instruction.

A single instruction, multiple data (SIMD) processor, comprising:

• a compute array having one or more processing element that includes a register set divisible into a number of SIMD lanes;
• and
• one or more mask registers having a number of mask bits, such that each SIMD lane has at least one corresponding mask bit,
• wherein the one or more processing elements are operable to:
• set each of the mask bits to a first state or a second state when a loop count of a loop of an operation associated with an instruction indicates that the operation is in a last iteration of the loop, and set all of the mask bits to the first state otherwise,
• enable the SIMD lanes having corresponding mask bits of the first state to execute the instruction, and
• disable the SIMD lanes having corresponding mask bits of the second state from executing the instruction.

An apparatus comprising:

• means for issuing an instruction to one or more processing elements that include one or more registers divisible into processing lanes for parallel processing;
• means for setting each of mask bits corresponding with the processing lanes to a first state or a second state when a loop count of a loop of an operation associated with the instruction indicates that the operation is in a last iteration of the loop, and setting all of the mask bits to the first state otherwise;
• means for enabling processing lanes having corresponding mask bits of the first state to execute the instruction;
• and
• means for disabling processing lanes having corresponding mask bits of the second state from executing the instruction.