G06F 9/3867
Using instruction pipelines
Official title: {using instruction pipelines}
G06F9/3867 (Using instruction pipelines) appears on 2,824 US grants and 2,576 published applications in this corpus.
Search patents in G06F- Granted patents
- 2,824
- Published applications
- 2,576
- Assignees
- 590
- Inventors
- 4,401
- Latest grant
- 6 Oct 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1978 | 4 | 0 |
| 1979 | 0 | 0 |
| 1980 | 3 | 0 |
| 1981 | 4 | 0 |
| 1982 | 4 | 0 |
| 1983 | 4 | 0 |
| 1984 | 3 | 0 |
| 1985 | 3 | 0 |
| 1986 | 8 | 0 |
| 1987 | 9 | 0 |
| 1988 | 10 | 0 |
| 1989 | 8 | 0 |
| 1990 | 4 | 0 |
| 1991 | 16 | 0 |
| 1992 | 17 | 0 |
| 1993 | 14 | 0 |
| 1994 | 18 | 0 |
| 1995 | 32 | 0 |
| 1996 | 58 | 0 |
| 1997 | 46 | 0 |
| 1998 | 106 | 0 |
| 1999 | 77 | 0 |
| 2000 | 83 | 0 |
| 2001 | 62 | 25 |
| 2002 | 56 | 70 |
| 2003 | 64 | 81 |
| 2004 | 55 | 98 |
| 2005 | 62 | 65 |
| 2006 | 86 | 103 |
| 2007 | 74 | 82 |
| 2008 | 78 | 121 |
| 2009 | 58 | 113 |
| 2010 | 73 | 60 |
| 2011 | 100 | 40 |
| 2012 | 69 | 51 |
| 2013 | 51 | 64 |
| 2014 | 56 | 90 |
| 2015 | 56 | 106 |
| 2016 | 101 | 79 |
| 2017 | 110 | 170 |
| 2018 | 84 | 99 |
| 2019 | 113 | 109 |
| 2020 | 125 | 154 |
| 2021 | 156 | 155 |
| 2022 | 146 | 152 |
| 2023 | 141 | 118 |
| 2024 | 143 | 121 |
| 2025 | 106 | 97 |
| 2026 | 68 | 153 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Subgroups
Granted patents
Recent patents
- Cache structure and utilization6 Oct 2026US 12,754,876 B2Intel Corporation
- Cloud platform based data mesh architecture for data pipelines6 Oct 2026US 12,756,620 B1Humana Inc.
- Arithmetic processing apparatus which executes plurality of instructions in parallel and sequentially from executable instructions and method for arithmetic processing29 Sep 2026US 12,748,598 B2Fujitsu Limited
- Data exchanging method of pipeline elements and non-transitory computer readable medium29 Sep 2026US 12,748,601 B2Adlink Technology Inc.
- Power savings during parallel synchronization for distributed memory systems by using different processor states22 Sep 2026US 12,743,282 B2Dell Products L. P.
- Inserting null vectors into a stream of vectors8 Oct 2026US 2026/0310466 A1Texas Instruments Incorporated
- Hardware-Assisted Dynamic Register Allocation8 Oct 2026US 2026/0310610 A1MIPS Tech, LLC
- Task delegation24 Sep 2026US 2026/0288464 A1Arm Limited
- Maintaining state information24 Sep 2026US 2026/0288467 A1Arm Limited
- Cache coherence shared state suppression24 Sep 2026US 2026/0288640 A1
Most cited
By later US patents
- Vector processor system420US 8,356,144 B22013
- Processor having plurality of functional units for orderly retiring outstanding operations based upon its associated tags403US 5,226,126 ANexgen Microsystems · 1993
- DRAM with high bandwidth interface that uses packets and arbitration313US 5,778,419 AMicroUnity Systems Engineering, Inc. · 1998
- RISC architecture computer configured for emulation of the instruction set of a target computer288US 5,574,927 AInternational Meta Systems, Inc. · 1996
- Microprocessor having software controllable power consumption272US 5,996,083 AHewlett-Packard Company · 1999