Power savings during parallel synchronization for distributed memory systems by using different processor states
AssigneeDell Products L.P.
InventorMartin Hilgeman
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AssigneeDell Products L.P.
InventorMartin Hilgeman
Estimating the term…
Presented herein are embodiments that involve the CPU-intensive nature of parallel applications using message passing on multiple, distributed-memory server nodes. Power saving embodiments may be integrated into existing HPC (high-performance computing) applications using a message passing interface, which may be implemented using a software library. Tested embodiments showed savings of up to 17% of power consumption at the expense of a small performance penalty. In at least one case, an actual performance improvement was seen. It shall be noted that embodiments are not limited to parallel HPC workloads. One or more embodiments may be extended to every workload where either load imbalance or wait time for external data is involved, like shared storage systems, and distributed network operations for artificial intelligence/machine learning workloads.
A processor-implemented method comprising:
An information handling system comprising:
A non-transitory computer-readable medium or media comprising one or more sequences of instructions which, when executed by at least one processor, causes steps to be performed comprising:
Dependencies are inferred from the claim text.