Arithmetic processing apparatus which executes plurality of instructions in parallel and sequentially from executable instructions and method for arithmetic processing

A method for arithmetic processing in an arithmetic processing apparatus that executes a plurality of instructions in parallel and sequentially from executable instructions, the method comprising:

• at a scheduler provided in the arithmetic processing apparatus,
• storing, in a queue, the plurality of instructions being accepted;
• and
• holding an indicator indicating a pipeline that executes a producer instruction included in the plurality of instructions stored in the queue and uniquely identifying an execution stage on the pipeline of the producer instruction from which a result of an operation is to be forwarded, the pipeline having multiple types of latency;
• executing data dependency resolution between the producer instruction and a consumer instruction that uses an execution result of the producer instruction and that is included in the plurality of instructions;
• and
• controlling issuing timings of the plurality of instructions,
• wherein the storing comprises storing, in the queue, a plurality of consumer instructions, and
• wherein the holding comprises holding a plurality of indicators each indicating the pipeline of the producer instruction for each of the plurality of consumer instructions,
• wherein the indicator comprises:
• pipeline identification information of the pipeline to which the producer instruction is issued;
• and
• stage identification information uniquely allocated to each stage, from a stage corresponding to a first issuing timing at which the result of the operation is forwarded from the producer instruction to the consumer instruction at a shortest forwarding timing to a stage corresponding to a second issuing timing at which the result of the arithmetic operation is stored in a register and comes to be ready to be read by the consumer instruction, and
• wherein:
• the stage identification information is set at a first cycle earlier by a first given number of cycles than a last cycle at which the producer instruction is executed, and is reset at a second cycle later by a second given number of cycles than the last cycle;
• and
• unique identifiers are allocated one to each of one or more cycles from the first cycle to the second cycle.