Task delegation

The apparatus as claimed in claim 21, wherein the data processing pipeline comprises a set of registers for holding data values on which the data processing operations are performed and;

• the decoding circuitry is responsive to an extension synchronisation instruction to:
• generate the control signals to determine whether the extension processing circuitry has completed the delegated task;
• and
• generate the control signals to control the extension processing circuitry to pass at least one result data value to at least one result register of the set of registers, when the extension processing circuitry has completed the delegated task.

The apparatus as claimed in claim 21, wherein the data processing pipeline comprises a set of registers for holding data values on which the data processing operations are performed;

• further comprising multiple instances of extension processing circuitry associated with the data processing pipeline and each instance is capable of performing the delegated task in response to the delegation signal received from the data processing pipeline,
• wherein the extension start instruction specifies an allocated extension register of the set of registers, and wherein the decoding circuitry is responsive to the extension start instruction to generate the control signals:
• to cause the delegated task to be allocated to a selected instance of the extension processing circuitry;
• and
• to control the data processing pipeline to write an identifier of the selected instance of the extension processing circuitry to the allocated extension register.

The apparatus as claimed in claim 21, wherein the data processing pipeline comprises a set of registers for holding data values on which the data processing operations are performed;

• the apparatus comprises multiple instances of extension processing circuitry associated with the data processing pipeline and each instance is capable of performing the delegated task in response to the delegation signal received from the data processing pipeline, and
• the decoding circuitry is responsive to an extension event instruction specifying an event-indicating register of the set of registers to:
• generate the control signals to control the data processing pipeline to identify an instance of extension processing circuitry that has completed the delegated task;
• and
• generate the control signals to cause an identifier of the instance of extension processing circuitry that has completed the delegated task to be written to the event-indicating register.

A method of data processing, comprising:

• performing data processing operations in a data processing pipeline in dependence on a received sequence of instructions;
• performing a delegated task in extension processing circuitry associated with the data processing pipeline in response to a delegation signal received from the data processing pipeline;
• decoding in decoding circuitry the received sequence of instructions generate control signals to control the data processing pipeline to perform the data processing operations,
• wherein the decoding is responsive to an extension start instruction specifying the delegated task to:
• generate the control signals to control the data processing pipeline to issue the delegation signal to the extension processing circuitry to delegate the delegated task to the extension processing circuitry;
• and
• performing the delegated task in the extension processing circuitry asynchronously to the data processing operations performed by data processing pipeline.

A computer program for controlling a host data processing apparatus to provide an instruction execution environment, the computer program comprising:

• data processing pipeline logic for performing data processing operations in dependence on a received sequence of instructions;
• and
• extension processing logic associated with the data processing pipeline logic and configured to perform a delegated task in response to a delegation signal received from the data processing pipeline logic,
• wherein the data processing pipeline logic comprises decoding logic configured to decode the received sequence of instructions and to generate control signals to control the data processing pipeline logic to perform the data processing operations,
• wherein the decoding circuitry is responsive to an extension start instruction specifying the delegated task to:
• generate the control signals to control the data processing pipeline logic to issue the delegation signal to the extension processing logic to delegate the delegated task to the extension processing logic, and
• wherein the extension processing logic is configured to perform the delegated task asynchronously to the data processing operations performed by data processing pipeline logic.