Microprocessor having software controllable power consumption

A computer having internal power management features comprising:

• a microprocessor having a plurality of functional units within the microprocessor, a power control register within the microprocessor having a plurality of power register fields, each field corresponding to a corresponding one of the functional units;
• a memory coupled to the microprocessor for storing instructions executable by the microprocessor;
• executable code stored in the memory, the microprocessor being responsive to the code to store values in each of the power register fields for individually controlling the level of power consumption of one of the functional units according to its corresponding power register field;
• and
• power control logic circuitry configured to independently adjust the rate of execution of each one of the functional units having a corresponding power register field responsive to the value stored in the corresponding power register field so that the power dissipated by each of the functional units is independently adjusted by the value stored in the corresponding power register field.

A computer having internal power management features comprising:

• a microprocessor having a plurality of functional units within the microprocessor, a power control register within the microprocessor having a plurality of power control register fields, each field corresponding to a corresponding one of the functional units;
• a memory coupled to the microprocessor for storing instructions executable by the microprocessor;
• executable code stored in the memory, the microprocessor being responsive to the code to store values in the power control register fields for independently controlling the level of power consumption of the corresponding functional units;
• power control logic circuitry configured to adjust the rate of execution of each one of the functional units having a corresponding power control register field responsive to the value stored in the corresponding power control register field so that the power dissipated by the corresponding functional unit is independently adjusted by the value in the corresponding power control register;
• and
• a buffer configured to reduce the width of a data bus interface from a first number of bits to a second number of bits responsive to the value stored in one of the plurality of power control register fields.

A method of minimizing power consumption in a computer including a microprocessor having a plurality of functional units within the microprocessor, the method comprising:

• providing the microprocessor with a power control register within the microprocessor having a plurality of fields, each field corresponding to a functional unit;
• using software or firmware to independently vary a value in each power register field responsive to the nature of an instruction to be executed by the microprocessor;
• and
• adjusting the rate of execution of one of the functional units in accordance with the value stored in the corresponding field in order to adjust the power consumed by the microprocessor.

A method of minimizing power consumption in a computer including a microprocessor having a plurality of functional units within the microprocessor, the method comprising:

• providing the microprocessor with a power control register within the microprocessor having a plurality of fields, each field corresponding to a functional unit;
• storing a value in each power register field responsive to an instruction executed by the microprocessor;
• and
• adjusting the rate of execution of one of the functional units in accordance with the value stored in the corresponding field in order to adjust the power consumed by the microprocessor
• wherein;
• storing a value in each power register field includes imbedding into code for a program to be executed by the microprocessor, instructions which control rate of execution of the functional units;
• and
• adjusting the rate of execution of one of the functional units in accordance with the value stored in the corresponding field includes
• responsive to a first of said instructions, adjusting the rate of execution of a selected one of the functional units to reduce its power consumption while other functional units execute the program according to code corresponding to said units, and
• responsive to a second of said instructions adjusting the rate of execution of the selected functional unit to full power to execute a portion of the code executable by the selected functional unit.

A method for controlling power consumption of a plurality of functional units in a microprocessor, the method comprising:

• coupling power control circuitry to the plurality of functional units, the power control circuitry being adapted to individually adjust the power consumption of each one of the plurality of functional units;
• coupling a power control register having a plurality of fields to the power control circuitry, where each one of the plurality of field of the power control register corresponds to one of the plurality of functional units;
• independently adjusting the power consumption of each one of the plurality of functional units responsive to a value in the corresponding field of the power control register;
• and
• setting the value in each one of the fields of the power control register responsive to a computer executable instruction.