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US 2026/0288640 A1Published application
Cache coherence shared state suppression
OwnerAbhijeet Ashok CHACHAD, David Matthew THOMPSON +2inventors
InventorsAbhijeet Ashok CHACHAD, David Matthew THOMPSON, Timothy David ANDERSON, Kai CHIRCA
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Abstract
A method includes receiving, by a level two (L2) controller, a first request for a cache line in a shared cache coherence state; mapping, by the L2 controller, the first request to a second request for a cache line in an exclusive cache coherence state; and responding, by the L2 controller, to the second request.
Claims20
A system, comprising:
- a memory;
- a first memory controller;
- and
- a second memory controller associated with the memory and coupled to the first memory controller, wherein the second memory controller is configured to:
- receive a first request from the first memory controller, wherein the first request is associated with a first state for a set of data;
- and
- determine whether to generate a second request associated with a second state for the set of data based on the first state and the first request.
4 more elements
A method, comprising:
- determining to change a size of a first memory by a first memory controller;
- executing pending requests from a processor by the first memory controller;
- stalling new requests from the processor by the first memory controller;
- writing back and invalidating a set of entries in the first memory by the first memory controller;
- providing an indication that the first memory has been invalidated and its changed size to a second memory controller by the first memory controller;
- providing a corresponding set of coherent states of the set of entries to the second memory controller by the first memory controller;
- in response to a hit of the set of entries in a third memory, update a copy of the corresponding set of coherent states stored in a second memory by the second memory controller;
- and
- in response to receiving the indication, clearing and resizing a third memory to match the changed size of the first memory by the second memory controller.
6 more elements
A device, comprising:
- a first memory having a first set of data at a first location;
- a second memory having a second set of data at a second location;
- a third memory;
- a first memory controller coupled to the first, second, and third memories, wherein the first memory controller is configured to:
- write a third set of data to the first location;
- write the first set of data to the second location;
- and
- write the second set of data to the third memory;
- a fourth memory having a copy of the first set of data at a third location;
- a fifth memory having a copy of the second set of data at a fourth location;
- a second memory controller coupled to the first memory controller and the fourth and fifth memories, wherein the second memory controller is configured to:
- receive a request from the first memory controller;
- in response to the request, write a copy of the third set of data to the third location;
- receive a copy of the second set of data from the first memory controller;
- and
- write the copy of the second set of data to the fifth memory.
13 more elements
Dependencies are inferred from the claim text.