G06F 9/3816
Instruction alignment
Official title: {Instruction alignment, e.g. cache line crossing}
G06F9/3816 (Instruction alignment) appears on 516 US grants and 284 published applications in this corpus.
Search patents in G06F- Granted patents
- 516
- Published applications
- 284
- Assignees
- 121
- Inventors
- 815
- Latest grant
- 1 Sep 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1980 | 1 | 0 |
| 1981 | 0 | 0 |
| 1982 | 0 | 0 |
| 1983 | 0 | 0 |
| 1984 | 1 | 0 |
| 1985 | 3 | 0 |
| 1986 | 1 | 0 |
| 1987 | 2 | 0 |
| 1988 | 1 | 0 |
| 1989 | 3 | 0 |
| 1990 | 1 | 0 |
| 1991 | 2 | 0 |
| 1992 | 6 | 0 |
| 1993 | 2 | 0 |
| 1994 | 5 | 0 |
| 1995 | 10 | 0 |
| 1996 | 20 | 0 |
| 1997 | 22 | 0 |
| 1998 | 44 | 0 |
| 1999 | 50 | 0 |
| 2000 | 28 | 0 |
| 2001 | 31 | 2 |
| 2002 | 19 | 10 |
| 2003 | 17 | 11 |
| 2004 | 10 | 26 |
| 2005 | 10 | 27 |
| 2006 | 10 | 14 |
| 2007 | 20 | 11 |
| 2008 | 23 | 19 |
| 2009 | 9 | 7 |
| 2010 | 12 | 10 |
| 2011 | 12 | 4 |
| 2012 | 5 | 7 |
| 2013 | 9 | 18 |
| 2014 | 12 | 9 |
| 2015 | 12 | 7 |
| 2016 | 4 | 6 |
| 2017 | 12 | 3 |
| 2018 | 4 | 4 |
| 2019 | 5 | 9 |
| 2020 | 9 | 18 |
| 2021 | 14 | 12 |
| 2022 | 11 | 8 |
| 2023 | 13 | 16 |
| 2024 | 14 | 10 |
| 2025 | 11 | 10 |
| 2026 | 6 | 6 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Chiplet-integrated machine learning accelerators1 Sep 2026US 12,724,732 B2Advanced Micro Devices, Inc.
- Cache line invalidation technologies7 Jul 2026US 12,675,413 B2Intel Corporation
- Silent cache line eviction26 May 2026US 12,639,228 B2Micron Technology, Inc.
- Operating system pagesize compatibility workarounds21 Apr 2026US 12,608,209 B2Arm Limited
- Compiler algorithm for GPU prefetching31 Mar 2026US 12,591,433 B2QUALCOMM Incorporated
- Chiplet-integrated machine learning accelerators24 Sep 2026US 2026/0288661 A1Advanced Micro Devices, Inc.
- Systems and methods for generating aligned data from segmented data channels17 Sep 2026US 2026/0277613 A1Advanced Micro Devices, Inc.
- Variable-length instruction set mode30 Jul 2026US 2026/0219888 A1Arm Limited
- Container-based instruction set30 Jul 2026US 2026/0219890 A1Arm Limited
- Misaligned memory accesses to an address-sliced cache18 Jun 2026US 2026/0169748 A1Intel Corporation
Most cited
By later US patents
- Pipelined data processor capable of decoding and executing plural instructions in parallel341US 4,858,105 AHitachi, Ltd. · 1989
- Cluster architecture for a highly parallel scalar/vector multiprocessor system255US 5,197,130 ASupercomputer Systems Limited Partnership · 1993
- Method for pipeline processing of instructions by controlling access to a reorder buffer using a register file outside the reorder buffer215US 5,721,855 AIntel Corporation · 1998
- Data cache which speculatively updates a predicted data cache storage location with store data and subsequently corrects mispredicted updates200US 5,860,104 AAdvanced Micro Devices, Inc. · 1999
- Data processing unit with pipelined operands145US 4,454,578 AHitachi, Ltd. · 1984