Cache line invalidation technologies

An apparatus comprising:

• a device to be coupled to a processor by a device interface, wherein the device comprises:
• circuitry, wherein the circuitry is to receive a descriptor, wherein the descriptor comprises a command that is to cause the circuitry to read data associated with a memory address range and cause invalidation of multiple cache lines associated with the memory address range in a cache device, wherein the cache device is associated with the processor, wherein the processor comprises one or more of a central processing unit (CPU), core, or graphics processing unit (GPU), and wherein the descriptor is to request the device to transmit a packet that includes the data stored in the multiple cache lines that are to be invalidated.

At least one non-transitory computer-readable medium comprising instructions stored thereon, that if executed by one or more processors, cause the one or more processors to:

• execute an operating system (OS) to:
• configure circuitry with one or more permitted requesters and
• enable invalidation of multiple cache lines of a cache device associated with a memory address range based on a command received from a device that requests a read of data from the multiple cache lines and invalidation of the multiple cache lines and based on the command being provided by a permitted requester among the one or more permitted requesters, wherein the cache device is associated with a processor, wherein the processor comprises one or more of a central processing unit (CPU), core, or graphics processing unit (GPU), wherein a descriptor includes the command, and wherein the descriptor is to request the device to transmit a packet that includes the data stored in the multiple cache lines that are to be invalidated.