Compiler algorithm for GPU prefetching

A method comprising:

• determining if an exposed latency parameter is greater than zero;
• determining that a loop is present in a program code;
• determining that the exposed latency parameter is greater than zero;
• determining that access overlap across fibers is true;
• and
• executing a prefetch instruction every quantity K fibers of at least one cache line size at a prefetch distance D with a maximum of quantity N iterations to reduce memory latency.

A method comprising:

• determining that a loop is not present in a program code;
• determining that an exposed latency parameter is greater than zero;
• determining that access overlap across fibers is true;
• and
• a prefetch instruction every quantity K fibers of at least one cache line size at a prefetch distance D or executing a prefetch instruction per fiber of at least one cache line size at a prefetch distance D to reduce memory latency.

A non-transitory computer-readable medium storing computer executable code, operable on a device comprising at least one processor and at least one memory coupled to the at least one processor, wherein the at least one processor is configured to implement a processor prefetching, the computer executable code comprising:

• instructions for causing a computer to determine if an exposed latency parameter is greater than zero;
• instructions for causing the computer to determine if a loop is present in a program code;
• instructions for causing the computer to determine if access overlap across fibers is true;
• and
• instructions for causing the computer to perform one of the following:
• a) execute a prefetch instruction every quantity K fibers at a prefetch distance D wherein, the prefetch distance D is equal to an exposed latency parameter divided by an average instruction latency parameter and the quantity K is equal to a cache line size divided by a per fiber access size;
• b) execute a prefetch instruction every quantity K fibers with a maximum of quantity N iterations, wherein the quantity N is equal to an exposed latency parameter divided by an average iteration latency parameter, and the quantity K is equal to a cache line size divided by a per fiber access size;
• or
• c) execute a prefetch per fiber with a maximum of quantity N iterations ahead, wherein the quantity N is equal to an exposed latency parameter divided by the average iteration latency parameter to reduce memory latency.