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US 12,724,732 B2Granted
Chiplet-integrated machine learning accelerators
AssigneeAdvanced Micro Devices, Inc.
InventorsSwapnil P. Sakharshete, Andrew S. Pomianowski, Maxim V. Kazakov, Vineet Goel, Milind N. Nemlekar, Skyler Jonathon Saleh
Life of this patent
Estimating the term…
Abstract
Techniques for performing machine learning operations are provided. The techniques include configuring a first portion of a first chiplet as a cache; performing caching operations via the first portion; configuring at least a first sub-portion of the first portion of the chiplet as directly-accessible memory; and performing machine learning operations with the first sub-portion by a machine learning accelerator within the first chiplet.
Claims18
A method comprising:
- performing caching operations for a graphics accelerator via a first portion of a cache that is present in a first chiplet, the first chiplet acting as an interface between the graphics accelerator and a system memory, the caching operations being performed as part of a cache hierarchy of the graphics accelerator,
- in response to a request for additional directly-accessible memory for use by an accelerator of the first chiplet, reconfiguring at least a first sub-portion of the first portion of the cache from being used as a cache to be used as directly-accessible memory, wherein the accelerator is configured to perform machine learning operations and to store input operands and output results into the directly-accessible memory;
- accessing the first sub-portion by the accelerator within the first chiplet, wherein the accessing includes the accelerator explicitly requesting data be stored into or loaded from the first sub-portion, the explicitly requesting specifying an address within the first sub-portion;
- and
- transmitting data to or receiving data from a second chiplet that is physically separate from a processing core that requests the first chiplet to perform machine learning operations, wherein the data is transmitted or received via a direct connection between the first chiplet and the second chiplet that does not flow through the processing core.
2 more elements
A device comprising:
- one or more machine learning accelerators;
- and
- a chiplet memory of a first chiplet, configured to;
- perform caching operations via a first portion of a cache that is present in the chiplet memory of the first chiplet, the first chiplet acting as an interface between an accelerator and a system memory, the caching operations being performed as part of a cache hierarchy of the accelerator;
- in response to a request for additional directly-accessible memory, for use by an accelerator, within the chiplet memory, reconfigure at least a first sub-portion of the first portion of the cache from being used as a cache to being used as directly-accessible memory, wherein the accelerator is configured to perform machine learning operations and to store input operands and output results into the directly-accessible memory;
- access the first sub-portion by the accelerator, wherein the accessing includes the accelerator explicitly requesting data be stored into or loaded from the first sub-portion, the explicitly requesting specifying an address within the first sub-portion;
- and
- transmit data to or receiving data from a second chiplet that is physically separate from a processing core that requests the first chiplet to perform machine learning operations, wherein the data is transmitted or received via a direct connection between the first chiplet and the second chiplet that does not flow through the processing core.
5 more elements
A device, comprising:
- a first chiplet including
- a first chiplet memory and a first set of one or more machine learning accelerators;
- a second chiplet;
- and
- a processing core,
- wherein the first chiplet is configured to:
- perform caching operations via a first portion of a cache that is present in the first chiplet, the first chiplet acting as an interface between an accelerator and a system memory, the caching operations being performed as part of a cache hierarchy of the accelerator;
- in response to a request for additional directly-accessible memory for use by an accelerator within the first chiplet memory, reconfigure at least a first sub-portion of the first portion of the cache from being used as a cache to be used memory as directly-accessible memory, wherein the accelerator is configured to perform machine learning operations and to store input operands and output results into the directly-accessible memory;
- access the first sub-portion by the accelerator, wherein the accessing includes the accelerator explicitly requesting data be stored into or loaded from the first sub-portion, the explicitly requesting specifying an address within the first sub-portion;
- and
- transmit data to or receiving data from a second chiplet that is physically separate from a processing core that requests the first chiplet to perform machine learning operations, wherein the data is transmitted or received via a direct connection between the first chiplet and the second chiplet that does not flow through the processing core.
8 more elements
Dependencies are inferred from the claim text.