Misaligned memory accesses to an address-sliced cache

Abstract

Techniques for misaligned memory to accesses an address-sliced cache are described. In an embodiment, an apparatus includes a data cache; and a memory execution unit to access the data cache, the memory execution unit including multiple slice portions, wherein each slice portion is to perform memory access operations for a corresponding address range, and wherein a first slice portion includes low-split circuitry to perform a one or more low-split operations for a low-order portion of a data value and a second slice portion includes high-split circuitry to perform one or more high-split operations for a high-order portion of the data value.

Dependencies are inferred from the claim text.