Data processing unit with pipelined operands

A data processing unit for executing variable length instructions in which operand specifiers for specifying addressing modes of operands are independent from operation codes for ascertaining operations, comprising:

• (A) instruction fetch means connected to memory means for storing instructions and operands, said instruction fetch means including:
• (1) instruction buffer means connected to said memory means, for retaining instructions prefetched from said memory means,
• (3) a fetch pointer connected to said memory means for applying to said memory means an address of an instruction to be prefetched into said instruction buffer means, and
• (3) instruction alignment means connected to said instruction buffer means, for aligning bit sequences of instructions prefetched from said memory means in the order of their address, for outputting a bit sequence including an operation code and at least one operand specifier in a first decode cycle, and for outputting a bit sequence including at least one operand specifier in a succeeding decode cycle;
• (B) instruction decoding means connected to said instruction fetch means, said instruction decoding means including:
• (1) operation code decoding means connected to said instruction alignment means for ascertaining the operand specifiers included in instruction aligned by said instruction alignment means and ascertaining the function of said instruction, and
• (2) operand specifier decoding means connected to said instruction alignment means for decoding one or more operand specifiers aligned by said instruction alignment means in the same machine cycle, and
• (C) address calculation means connected to said decoding means for calculating an effective address of the operand in accordance with an operation code and operand specifiers decoded by said decoding means in the previous machine cycle,
• whereby said instruction fetch means carries out instruction fetching independently of the instruction decoding means and of the address calculation means, said instruction decoding means operates, utilizing an operand specifier as a basic processing unit of, independently of the instruction fetch means and of the address calculation means, and said address calculation means operates, utilizing an operand specifier as a basic unit of processing, independently of the instruction fetch means and of the instruction decoding means, thereby carrying out pipelined processing based on a unit of one or more than one simultaneously processed operand specifiers.