G06F 9/30145
Instruction analysis
Official title: {Instruction analysis, e.g. decoding, instruction word fields}
G06F9/30145 (Instruction analysis) appears on 4,890 US grants and 4,536 published applications in this corpus.
Search patents in G06F- Granted patents
- 4,890
- Published applications
- 4,536
- Assignees
- 672
- Inventors
- 5,915
- Latest grant
- 6 Oct 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1976 | 5 | 0 |
| 1977 | 3 | 0 |
| 1978 | 3 | 0 |
| 1979 | 4 | 0 |
| 1980 | 4 | 0 |
| 1981 | 7 | 0 |
| 1982 | 10 | 0 |
| 1983 | 9 | 0 |
| 1984 | 15 | 0 |
| 1985 | 8 | 0 |
| 1986 | 8 | 0 |
| 1987 | 10 | 0 |
| 1988 | 10 | 0 |
| 1989 | 15 | 0 |
| 1990 | 12 | 0 |
| 1991 | 16 | 0 |
| 1992 | 29 | 0 |
| 1993 | 31 | 0 |
| 1994 | 29 | 0 |
| 1995 | 52 | 0 |
| 1996 | 73 | 0 |
| 1997 | 76 | 0 |
| 1998 | 162 | 0 |
| 1999 | 143 | 0 |
| 2000 | 107 | 0 |
| 2001 | 114 | 26 |
| 2002 | 86 | 75 |
| 2003 | 79 | 81 |
| 2004 | 77 | 124 |
| 2005 | 70 | 99 |
| 2006 | 69 | 94 |
| 2007 | 75 | 88 |
| 2008 | 85 | 125 |
| 2009 | 66 | 119 |
| 2010 | 93 | 73 |
| 2011 | 87 | 97 |
| 2012 | 64 | 101 |
| 2013 | 96 | 202 |
| 2014 | 105 | 228 |
| 2015 | 152 | 277 |
| 2016 | 309 | 318 |
| 2017 | 289 | 332 |
| 2018 | 260 | 225 |
| 2019 | 294 | 336 |
| 2020 | 284 | 299 |
| 2021 | 297 | 246 |
| 2022 | 260 | 260 |
| 2023 | 242 | 202 |
| 2024 | 197 | 210 |
| 2025 | 198 | 171 |
| 2026 | 101 | 128 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Subgroups
Granted patents
Recent patents
- Circuitry and methods for implementing forward-edge control-flow integrity (FECFI) using one or more capability-based instructions6 Oct 2026US 12,754,853 B2Intel Corporation
- Methods and apparatus to sequence analog to digital conversions29 Sep 2026US 12,748,595 B2Texas Instruments Incorporated
- Parallel instruction demarcator22 Sep 2026US 12,743,280 B2Onnivation LLC
- Technique for handling ordering constrained access operations15 Sep 2026US 12,737,185 B2Arm Limited
- Device, method, and system to determine a count of retired prefetch instructions15 Sep 2026US 12,737,275 B2Intel Corporation
- Control method and chip8 Oct 2026US 2026/0310463 A1Smarter Silicon (Shanghai) Technologies Co., Ltd.
- Processing-in-memory system including scale-up architecture8 Oct 2026US 2026/0310464 A1SK hynix Inc.
- Encoding and Decoding Variable Length Instructions8 Oct 2026US 2026/0310465 A1Imagination Technologies Limited
- Inserting null vectors into a stream of vectors8 Oct 2026US 2026/0310466 A1Texas Instruments Incorporated
- Combined load value and load address prediction1 Oct 2026US 2026/0299955 A1
Most cited
By later US patents
- Packet processing system including a policy engine having a classification unit624US 6,157,955 AIntel Corporation · 2000
- Multiple address-space data processor with addressable register and context switching470US 5,201,039 AMitsubishi Denki Kabushiki Kaisha · 1993
- System and method for controlling a highly parallel multiprocessor using an anarchy based scheduler for parallel execution thread scheduling448US 5,179,702 ASupercomputer Systems Limited Partnership · 1993
- Processor-cache system and method417US 9,047,193 B2Shanghai Xin Hao Micro Electronics Co. Ltd. · 2015
- Processor having plurality of functional units for orderly retiring outstanding operations based upon its associated tags403US 5,226,126 ANexgen Microsystems · 1993