G06F 9/3016
Decoding the operand specifier
Official title: {Decoding the operand specifier, e.g. specifier format}
G06F9/3016 (Decoding the operand specifier) appears on 2,049 US grants and 1,865 published applications in this corpus.
Search patents in G06F- Granted patents
- 2,049
- Published applications
- 1,865
- Assignees
- 359
- Inventors
- 2,668
- Latest grant
- 15 Sep 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1976 | 4 | 0 |
| 1977 | 2 | 0 |
| 1978 | 1 | 0 |
| 1979 | 2 | 0 |
| 1980 | 2 | 0 |
| 1981 | 4 | 0 |
| 1982 | 8 | 0 |
| 1983 | 2 | 0 |
| 1984 | 8 | 0 |
| 1985 | 2 | 0 |
| 1986 | 3 | 0 |
| 1987 | 5 | 0 |
| 1988 | 5 | 0 |
| 1989 | 8 | 0 |
| 1990 | 5 | 0 |
| 1991 | 8 | 0 |
| 1992 | 15 | 0 |
| 1993 | 14 | 0 |
| 1994 | 14 | 0 |
| 1995 | 24 | 0 |
| 1996 | 41 | 0 |
| 1997 | 42 | 0 |
| 1998 | 84 | 0 |
| 1999 | 77 | 0 |
| 2000 | 49 | 0 |
| 2001 | 58 | 14 |
| 2002 | 45 | 33 |
| 2003 | 37 | 42 |
| 2004 | 30 | 57 |
| 2005 | 30 | 46 |
| 2006 | 35 | 40 |
| 2007 | 36 | 37 |
| 2008 | 41 | 70 |
| 2009 | 35 | 57 |
| 2010 | 43 | 32 |
| 2011 | 45 | 37 |
| 2012 | 24 | 38 |
| 2013 | 24 | 75 |
| 2014 | 41 | 65 |
| 2015 | 51 | 64 |
| 2016 | 96 | 128 |
| 2017 | 107 | 189 |
| 2018 | 97 | 116 |
| 2019 | 131 | 150 |
| 2020 | 132 | 119 |
| 2021 | 120 | 96 |
| 2022 | 87 | 82 |
| 2023 | 82 | 66 |
| 2024 | 76 | 86 |
| 2025 | 77 | 69 |
| 2026 | 40 | 57 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Subgroups
Granted patents
Recent patents
- Technique for handling ordering constrained access operations15 Sep 2026US 12,737,185 B2Arm Limited
- System and method enabling one-hot neural networks on a machine learning compute platform8 Sep 2026US 12,730,643 B2Intel Corporation
- Device, method and system to capture or restore microarchitectural state of a processor core8 Sep 2026US 12,730,645 B2Intel Corporation
- Method and apparatus for permuting streamed data elements8 Sep 2026US 12,730,758 B2Texas Instruments Incorporated
- Apparatus and method for managing deprecated instruction set architecture (ISA) features25 Aug 2026US 12,717,603 B2Intel Corporation
- Control method and chip8 Oct 2026US 2026/0310463 A1Smarter Silicon (Shanghai) Technologies Co., Ltd.
- Encoding and Decoding Variable Length Instructions8 Oct 2026US 2026/0310465 A1Imagination Technologies Limited
- Inserting null vectors into a stream of vectors8 Oct 2026US 2026/0310466 A1Texas Instruments Incorporated
- Systems, methods, and apparatuses for tile transpose24 Sep 2026US 2026/0288459 A1Intel Products IP LLC
- Task delegation24 Sep 2026US 2026/0288464 A1Arm Limited
Most cited
By later US patents
- Packet processing system including a policy engine having a classification unit624US 6,157,955 AIntel Corporation · 2000
- Multiple address-space data processor with addressable register and context switching470US 5,201,039 AMitsubishi Denki Kabushiki Kaisha · 1993
- Processor having plurality of functional units for orderly retiring outstanding operations based upon its associated tags403US 5,226,126 ANexgen Microsystems · 1993
- Dynamic multi-mode parallel processing array390US 5,475,856 AInternational Business Machines Corporation · 1995
- Real time processor capable of concurrently running multiple independent JAVA machines375US 6,374,286 B1Rockwell Collins, Inc. · 2002