G06F 9/30163
With implied specifier
Official title: {with implied specifier, e.g. top of stack}
G06F9/30163 (With implied specifier) appears on 156 US grants and 136 published applications in this corpus.
Search patents in G06F- Granted patents
- 156
- Published applications
- 136
- Assignees
- 67
- Inventors
- 316
- Latest grant
- 24 Feb 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1978 | 1 | 0 |
| 1979 | 0 | 0 |
| 1980 | 0 | 0 |
| 1981 | 2 | 0 |
| 1982 | 1 | 0 |
| 1983 | 0 | 0 |
| 1984 | 0 | 0 |
| 1985 | 0 | 0 |
| 1986 | 0 | 0 |
| 1987 | 0 | 0 |
| 1988 | 0 | 0 |
| 1989 | 0 | 0 |
| 1990 | 1 | 0 |
| 1991 | 0 | 0 |
| 1992 | 3 | 0 |
| 1993 | 0 | 0 |
| 1994 | 0 | 0 |
| 1995 | 2 | 0 |
| 1996 | 3 | 0 |
| 1997 | 3 | 0 |
| 1998 | 4 | 0 |
| 1999 | 15 | 0 |
| 2000 | 8 | 0 |
| 2001 | 10 | 2 |
| 2002 | 3 | 7 |
| 2003 | 6 | 4 |
| 2004 | 2 | 3 |
| 2005 | 1 | 6 |
| 2006 | 3 | 6 |
| 2007 | 2 | 5 |
| 2008 | 1 | 4 |
| 2009 | 4 | 6 |
| 2010 | 3 | 4 |
| 2011 | 3 | 5 |
| 2012 | 2 | 3 |
| 2013 | 2 | 5 |
| 2014 | 3 | 5 |
| 2015 | 3 | 3 |
| 2016 | 5 | 14 |
| 2017 | 13 | 5 |
| 2018 | 9 | 13 |
| 2019 | 12 | 12 |
| 2020 | 9 | 8 |
| 2021 | 3 | 3 |
| 2022 | 6 | 1 |
| 2023 | 3 | 4 |
| 2024 | 2 | 2 |
| 2025 | 2 | 3 |
| 2026 | 1 | 3 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Encoding and decoding variable length instructions24 Feb 2026US 12,561,139 B2Imagination Technologies Limited
- Coalescing adjacent gather/scatter operations15 Jul 2025US 12,360,774 B2Intel Corporation
- Implicit global pointer relative addressing for global memory access28 Jan 2025US 12,210,876 B2MIPS Tech, LLC
- Scalar core integration15 Oct 2024US 12,117,962 B2Intel Corporation
- Encoding and decoding variable length instructions9 Jan 2024US 11,868,775 B2Imagination Technologies Limited
- Encoding and Decoding Variable Length Instructions8 Oct 2026US 2026/0310465 A1Imagination Technologies Limited
- Method and apparatus for addressing registers within a processor based on indirect registers14 May 2026US 2026/0133798 A1International Business Machines Corporation
- Compact register specifiers for compact instruction encoding14 May 2026US 2026/0133801 A1Tuple Semiconductor, Inc.
- Encoding and decoding variable length instructions10 Jul 2025US 2025/0224958 A1Imagination Technologies Limited
- Implicit Global Pointer Relative Addressing for Global Memory Access24 Apr 2025US 2025/0130806 A1MIPS Tech, LLC
Most cited
By later US patents
- Data cache which speculatively updates a predicted data cache storage location with store data and subsequently corrects mispredicted updates200US 5,860,104 AAdvanced Micro Devices, Inc. · 1999
- System and method for extraction, alignment and decoding of CISC instructions into a nano-instruction bucket for execution by a RISC computer135US 5,438,668 ASeiko Epson Corporation · 1995
- System for translating non-native instructions to native instructions and combining them into a final bucket for processing on a host processor88US 5,619,666 ASeiko Epson Corporation · 1997
- System and method for conditional moving an operand from a source register to destination register87US 6,298,438 B1Advanced Micro Devices, Inc. · 2001
- System and method for conditionally moving an operand from a source register to a destination register85US 5,909,572 AAdvanced Micro Device, Inc. · 1999