Compact register specifiers for compact instruction encoding

A system, comprising:

• an instruction register having one or more register address computation fields, each register address computation field comprising an address sub-field and a register address offset sub-field;
• one or more register address compute units, each register address compute unit enabled to receive a respective one of the register address computation fields and to use as inputs the register address sub-field and the register address offset sub-field of each of the respective one of the register address computation fields;
• and
• a register file having one or more access ports addressable by each of the one or more register address compute units.

A method, comprising:

• accessing a first register of a plurality of registers using first information of an instruction, the first information uniquely identifying a first any one of the plurality of registers;
• evaluating a function of (1) the first information and (2) second information of the instruction, a result of the evaluating uniquely identifying a second any one of the plurality of registers;
• and
• accessing a second register of the plurality of registers using the result.