Implicit global pointer relative addressing for global memory access

A computer program product embodied in a non-transitory computer readable medium for decoding instructions, the computer program product comprising code which causes one or more processors to perform operations of:

• receiving, at a decode unit, an instruction in a form for execution by an execution unit that specifies an operation to be performed, the received instruction being an instruction from an instruction set comprising one or more instructions, wherein at a time the received instruction is executed to perform the specified operation:
• the received instruction comprises an opcode that identifies the type of operation to be performed;
• the received instruction implicitly identifies a base register for the instruction;
• a total number of bits in the received instruction that implicitly identify the base register or identify the type of operation to be performed is less than a total number of bits that identify the base register or identify the type of operation to be performed in a corresponding instruction, for the same type of operation, that explicitly identifies the base register;
• and
• the instruction set comprises one or more instructions that identify a global pointer (GP) register as an operand of the instruction;
• decoding, at the decode unit, the received instruction to determine whether the received instruction is one of the one or more instructions that identify the GP register as an operand of the instruction;
• and
• in response to a determination that the received instruction is one of the one or more instructions from the instruction set that identify the GP register as an operand of the instruction, outputting one or more control signals to cause the execution unit to perform the specified operation with the GP register as an operand when the determination is positive.

A data processing apparatus comprising:

• a register file comprising a GP register, the GP register configured to store an address of global memory in which data is stored;
• an execution unit;
• and
• a decode unit configured to:
• receive an instruction in a form for execution by the execution unit that specifies an operation to be performed, the received instruction being an instruction from an instruction set comprising one or more instructions, wherein at a time the received instruction is executed to perform the specified operation:
• the received instruction comprises an opcode that identifies the type of operation to be performed;
• the received instruction implicitly identifies a base register for the instruction;
• a total number of bits in the received instruction that implicitly identify the base register or identify the type of operation to be performed is less than a total number of bits that identify the base register or identify the type of operation to be performed in a corresponding instruction, for the same type of operation, that explicitly identifies the base register;
• and
• the instruction set comprises one or more instructions that identify the GP register as an operand of the instruction;
• determine whether the received instruction is one of the one or more instructions that identify the GP register as an operand of the instruction;
• and
• in response to a determination that the received instruction is one of the one or more instructions from the instruction set that identify the GP register as an operand of the instruction, output one or more control signals to cause the execution unit to perform the specified operation with the GP register as an operand when the determination is positive.