Encoding and decoding variable length instructions
AssigneeImagination Technologies Limited
InventorsSimon Thomas Nield, James McCarthy
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Abstract
Methods of encoding and decoding are described which use a variable number of instruction words to encode instructions from an instruction set, such that different instructions within the instruction set may be encoded using different numbers of instruction words. To encode an instruction, the bits within the instruction are re-ordered and formed into instruction words based upon their variance as determined using empirical or simulation data. The bits in the instruction words are compared to corresponding predicted values and some or all of the instruction words that match the predicted values are omitted from the encoded instruction.
Claims20
A device for encoding instructions from an instruction set, the device comprising:
- a processor;
- and
- a memory arranged to store device-executable instructions configured when executed by the processor to cause the processor, in response to receiving an instruction from an instruction set, to:
- re-order and group bits in the received instruction into a plurality of instruction words according to an encoding type to generate an ordered sequence of instruction words;
- compare the instruction words in the ordered sequence to their corresponding predicted values;
- generate a compressed version of the instruction by omitting one or more of the instruction words in the ordered sequence based on the comparison between the instruction words in the ordered sequence and their corresponding predicted values;
- and
- output the compressed version of the instruction.
A device for decoding instructions from an instruction set, wherein different instructions within the instruction set are encoded with different numbers of instruction words, the device comprising:
- a processor;
- and
- a memory arranged to store device-executable instructions configured when executed by the processor to cause the processor, in response to receiving one or more fetched instruction words, to:
- generate an ordered sequence of instruction words by selecting, for each of the instruction words in the sequence, either a fetched instruction word or a predicted instruction word;
- concatenate the instruction words in the ordered sequence to form an encoded instruction and re-ordering bits in the encoded instruction according to a determined encoding type to generate a decoded instruction;
- and
- output the decoded instruction.
A device comprising:
- a processor;
- and
- a memory arranged to store device-executable instructions configured when executed by the processor to cause the processor, in response to receiving mapping data for an instruction set and instruction data describing instructions in an instruction set in canonical form, to:
- parse the mapping data and instruction data using a grammar library;
- generate both encoding software and a hardware description of a decoder based on the parsed mapping data and instruction data;
- and
- output the encoding software and the hardware description of a decoder;
- wherein the encoding software maps different instructions in the instruction set to different numbers of instruction words by, for each instruction of a plurality of instructions in the instruction set:
- re-ordering and grouping bits in the instruction into a plurality of instruction words according to an encoding type to generate an ordered sequence of instruction words;
- and
- comparing the instruction words in the ordered sequence to their corresponding predicted values and generating a compressed version of the instruction by omitting one or more of the instruction words in the ordered sequence based on the comparison.
Dependencies are inferred from the claim text.