US 5,438,668 AGranted

System and method for extraction, alignment and decoding of CISC instructions into a nano-instruction bucket for execution by a RISC computer

AssigneeSeiko Epson Corporation

InventorsBrett Coon, Yoshiyuki Miyayama, Le Trong Nguyen, Johannes Wang

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Abstract

A system and method for extracting complex, variable length computer instructions from a stream of complex instructions each subdivided into a variable number of instructions bytes, and aligning instruction bytes of individual ones of the complex instructions. The system receives a portion of the stream of complex instructions and extracts a first set of instruction bytes starting with the first instruction bytes, using an extract shifter. The set of instruction bytes are then passed to an align latch where they are aligned and output to a next instruction detector. The next instruction detector determines the end of the first instruction based on said set of instruction bytes. An extract shifter is used to extract and provide the next set of instruction bytes to an align shifter which aligns and outputs the next instruction. The process is then repeated for the remaining instruction bytes in the stream of complex instructions. The isolated complex instructions are decoded into nano-instructions which are processed by a RISC processor core.

Claims29

Dependent claims

A method for extracting complex, variable length computer instructions from a stream of complex instructions each subdivided into a variable number of instruction bytes, and aligning instruction bytes of individual ones of the complex instructions, comprising the steps of:

(1) receiving a portion of the stream of complex instructions;
(2) extracting a first set of instruction bytes starting with the first instruction bytes, using an extract shifter;
(3) passing said set of instruction bytes to an align latch;
(4) outputting the aligned instruction bytes from said align latch to a next instruction detector;
(5) determining the end of the first instruction based on said set of instruction bytes using said next instruction detector;
(6) controlling said extract shifter to extract and provide the next set of instruction bytes to an align shifter;
(7) controlling said align shifter to align and output the next instruction;
(8) latching said output of said align shifter in said align latch;
(9) outputting the aligned instruction bytes from said align latch to an instruction decode unit;
(10) decoding the aligned instruction bytes into one or more nano-instruction operations;
(11) placing said one or more nano-instruction operations into an instruction bucket;
(12) storing said instruction bucket in a first instruction latch or in a second instruction latch if said first instruction latch is not empty;
and
(13) combining the contents of said first and second instruction latches into a final instruction bucket on a nano-instruction-by-nano-instruction basis, wherein said combining comprises storing said first instruction latch nano-instruction operations into said final instruction bucket, and storing one or more of said second instruction latch nano-instruction operations into said final instruction bucket if said first instruction latch nano-instruction operations do not fill said final instruction bucket.

11 more elements

A system for decoding complex instruction set computer (CISC) instructions having a variable number of instruction bytes, into nano-instruction operations for processing on a reduced instruction set computer (RISC), the system comprising:

(a) first means for receiving complex instructions;
(b) second means, coupled to said first means, for decoding said complex instructions into one or more nano-instruction operations;
(c) third means, responsive to said second means, for placing said nano-instruction operations into an instruction bucket;
(d) fourth means, responsive to said third means, for storing said instruction bucket in one of a first instruction latch and a second instruction latch if said first instruction latch is not empty;
and
(e) fifth means, responsive to said fourth means, for combining the contents of said first and second instruction latches into a final instruction bucket on a nano-instruction-by-nano-instruction basis, wherein said combining comprises storing said first instruction latch nano-instruction operations into said final instruction bucket, and storing one or more of said second instruction latch nano-instruction operations into said final instruction bucket if said first instruction latch nano-instruction operations do not fill said final instruction bucket.

3 more elements

A method for decoding complex instruction set computer (CISC) instructions having a variable number of instruction bytes, into nano-instruction operations for processing on a reduced instruction set computer (RISC), the method comprising the steps of:

(1) receiving complex instructions;
(2) decoding said complex instructions into one or more nano-instruction operations;
(3) placing said nano-instruction operations into an instruction bucket;
(4) storing said instruction bucket in a first instruction latch or in a second instruction latch if said first instruction latch is not empty;
and
(5) combining the contents of said first and second instruction latches into a final instruction bucket on a nano-instruction-by-nano-instruction basis, wherein said combining comprises storing said first instruction latch nano-instruction operations into said final instruction bucket, and storing one or more of said second instruction latch nano-instruction operations into said final instruction bucket if said first instruction latch nano-instruction operations do not fill said final instruction bucket.

3 more elements

A system for extracting and aligning complex, variable length computer instructions from a stream of complex instructions, each complex instruction being subdivided into a variable number of instruction bytes, the system comprising:

(a) first means for receiving the stream of complex instructions;
(b) second means, responsive to said first means, for extracting instruction bytes from the stream of complex instructions;
(c) third means, responsive to said second means, for determining a number of the instruction bytes in said extracted instruction bytes that correspond to a first one of the complex instructions;
(d) fourth means, responsive to said third means, for aligning said first one of the complex instructions based on said number of corresponding instruction bytes, said fourth means comprising an align shifter for aligning complex instructions based on an align shift control signal;
(e) at least one align latch, wherein said align shifter outputs aligned complex instruction bytes to said at least one align latch;
wherein said third means comprises a next instruction detector for receiving said aligned complex instrsuction from said align latch, and determining and outputting the number of the instruction bytes in the complex instructions based on said aligned complex instruction bytes;
wherein said align shift control signal comprises the number of instruction bytes in a previous complex instruction determined by said next instruction detector, and said align shifter shifts said number of instruction bytes to thereby align furtehr instruction bytes corresponding to the next complex instruction,
wherein said align shifter then outputs said further instruction bytes corresponding to said next complex instruction to said at least one align latch;
and
(f) a prefix detector for receiving said aligned complex instruction bytes from said at least one align latch and determines the number of prefix bytes included at the beginning of said aligned complex instruction bytes.

7 more elements

Dependencies are inferred from the claim text.