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US 12,743,280 B2Granted
Parallel instruction demarcator
AssigneeOnnivation LLC
InventorSitaram Yadavalli
Life of this patent
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Abstract
Parallel instruction demarcators and methods for parallel instruction demarcation are included, wherein an instruction syllable sequence comprising a plurality of instruction syllables is received and stored at an instruction buffer. It is determined, using one or more logic blocks arranged in a sequence, a size of an instruction and at least one boundary at which the instruction is demarcated. Additionally, using a controlling logic block a restart point is determined from where the sequence of instruction syllables is examined and demarcated into individual instructions.
Claims30
An instruction demarcator comprising:
- a buffer to receive and store two or more instruction syllables,
- the two or more instruction syllables comprising a last stage instruction syllable in a first time cycle preceding a time boundary and a subsequent first stage instruction syllable in a second time cycle succeeding the time boundary;
- two or more logic blocks comprising a first logic block and a last logic block, wherein the first logic block comprises a first stage logic circuit and the last logic block comprises a last stage logic circuit, and
- wherein the first logic block receives a portion of the subsequent first stage instruction syllable in the second time cycle succeeding the time boundary and the last logic block receives a portion of the last stage instruction syllable in the first time cycle preceding the time boundary, and
- wherein the last logic block generates a first output of the last logic block;
- and
- a carryover storage entity comprising at least one storage element, and
- wherein the carryover storage entity receives, as input, the first output of the last logic block in the first time cycle preceding the time boundary, and
- wherein the first output of the last logic block is stored as a carryover value in the carryover storage entity by the end of the first time cycle preceding the time boundary,
- and wherein the carryover value in the carryover storage entity is transmitted in the second time cycle succeeding the time boundary, and
- wherein the carryover value from the carryover storage entity is received by the first logic block in the second time cycle succeeding the time boundary.
8 more elements
A method of demarcating instructions comprising:
- receiving two or more instruction syllables in a buffer, the two or more instruction syllables comprising a last stage instruction syllable received in a first time cycle preceding a time boundary and a subsequent first stage instruction syllable received in a second time cycle succeeding the time boundary;
- presenting a portion of the last stage instruction syllable received in the first time cycle preceding the time boundary to a last logic block of two or more logic blocks comprising a first logic block and the last logic block, wherein the first logic block comprises a first stage logic circuit and the last logic block comprises a last stage logic circuit, and
- presenting a portion of the subsequent first stage instruction syllable received in the second time cycle succeeding the time boundary to the first logic block, and
- wherein the last logic block generates a first output of the last logic block;
- and
- presenting the first output of the last logic block in the first time cycle preceding the time boundary as input to a carryover storage entity comprising at least one storage element, and
- wherein the first output of the last logic block is stored as a carryover value in the carryover storage entity by the end of the first time cycle preceding the time boundary,
- and wherein the carryover value in the carryover storage entity is transmitted in the second time cycle succeeding the time boundary, and
- wherein the carryover value from the carryover storage entity is received by the first logic block in the second time cycle succeeding the time boundary.
6 more elements
Dependencies are inferred from the claim text.