G06F 9/30109
Having multiple operands in a single register
Official title: {having multiple operands in a single register}
G06F9/30109 (Having multiple operands in a single register) appears on 611 US grants and 651 published applications in this corpus.
Search patents in G06F- Granted patents
- 611
- Published applications
- 651
- Assignees
- 140
- Inventors
- 895
- Latest grant
- 29 Sep 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1988 | 1 | 0 |
| 1989 | 0 | 0 |
| 1990 | 1 | 0 |
| 1991 | 1 | 0 |
| 1992 | 2 | 0 |
| 1993 | 0 | 0 |
| 1994 | 0 | 0 |
| 1995 | 1 | 0 |
| 1996 | 3 | 0 |
| 1997 | 3 | 0 |
| 1998 | 14 | 0 |
| 1999 | 11 | 0 |
| 2000 | 8 | 0 |
| 2001 | 17 | 4 |
| 2002 | 9 | 7 |
| 2003 | 9 | 11 |
| 2004 | 11 | 40 |
| 2005 | 8 | 23 |
| 2006 | 10 | 7 |
| 2007 | 17 | 6 |
| 2008 | 18 | 28 |
| 2009 | 11 | 28 |
| 2010 | 22 | 20 |
| 2011 | 22 | 20 |
| 2012 | 17 | 23 |
| 2013 | 24 | 51 |
| 2014 | 20 | 30 |
| 2015 | 35 | 34 |
| 2016 | 34 | 34 |
| 2017 | 40 | 34 |
| 2018 | 29 | 20 |
| 2019 | 30 | 43 |
| 2020 | 23 | 35 |
| 2021 | 39 | 25 |
| 2022 | 29 | 38 |
| 2023 | 28 | 27 |
| 2024 | 27 | 31 |
| 2025 | 27 | 17 |
| 2026 | 10 | 15 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Processor embedded streaming buffer29 Sep 2026US 12,748,592 B2Intel Corporation
- Computing system having an accumulator register having entries having a bit width larger than a main register file11 Aug 2026US 12,705,056 B2International Business Machines Corporation
- Segment load and stores4 Aug 2026US 12,699,564 B2Imagination Technologies Limited
- Processors, methods, systems, and instructions to select and store data elements from two source two-dimensional arrays indicated by permute control elements in a result two-dimensional array4 Aug 2026US 12,699,747 B2Intel Corporation
- Systems, apparatuses, and methods for chained fused multiply add14 Jul 2026US 12,681,724 B2Intel Corporation
- Systems, methods, and apparatuses for tile transpose24 Sep 2026US 2026/0288459 A1Intel Products IP LLC
- Method and apparatus for parallel pointer operations17 Sep 2026US 2026/0277609 A1Electronics and Telecommunications Research Institute
- System and method providing efficient packing of unaligned data9 Jul 2026US 2026/0195959 A1Intel Corporation
- Systems and methods for efficient execution of vector operations2 Jul 2026US 2026/0186776 A1Advanced Micro Devices, Inc.
- Fully homomorphic encryption (fhe) operations on a unified fhe accelerator2 Jul 2026US 2026/0189363 A1Intel Corporation
Most cited
By later US patents
- Method and system for efficient matrix multiplication in a SIMD processor architecture531US 7,873,812 B12011
- Running-min and running-max instructions for processing vectors using a base value from a key element of an input vector426US 8,417,921 B2Apple Inc. · 2013
- Three-dimensional vector processor222US 5,019,968 A1991
- Method and system for dynamically reconfiguring a register file in a vector processor204US 5,513,366 AInternational Business Machines Corporation · 1996
- SIMD datapath coupled to scalar/vector/address/conditional data register file with selective subpath scalar processing mode194US 6,839,828 B2International Business Machines Corporation · 2005