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US 5,019,968 AGranted
Three-dimensional vector processor
OwnerYulan Wang, Steven E. Butnerinventors
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Abstract
A robotics-control processor for performing real-time inverse kinematics and inverse dynamics calculations involving three-dimensional vectors. The processor employs a three-wide register and execution unit architecture, pipelined instructions, and register-to-register data processing to achieve rapid vector calculations. Broadcast buffers for exchanging operands between register files, and operand multiplexing at several levels within the processor allow program operation flexibility. In a preferred embodiment, the processor includes a CORDIC algorithm unit for rapid vector rotation and trigonometric function calculations.
Claims14
A processor for receiving and executing a series of program instructions and data provided from a memory, for carrying out vector/vector and scalar/vector arithmetic operations, comprising:
- a. a data transfer input means for receiving the series of program instructions and data from memory;
- b. I, J, and K register files coupled to said data transfer input mans for receiving operands therefrom, each containing a plurality of registers for storing scalar values for the components of a plurality of three-dimensional vectors;
- c. I, J, and K execution units coupled to said I, J, and K register files for performing arithmetic operations on operands placed in the execution units;
- d. I, J, and K operand pathways connecting each I, J, and K register file, respectively, with the corresponding I, J, and K execution units, for transferring operands stored in selected register locations to the corresponding execution units, in response to data-fetch commands carried in the program instructions, each said I, J, and K operand pathways including a first and second data bus;
- e. first and second broadcast buffer connecting I and J operand pathways and J and K operand pathways, respectively, for passing operands between each pair of the operand pathways, in response to pathway exchange commands carried in the program instructions;
- f. data-return means coupled to said I, J, and K execution units and said I, J, and K register files for returning operands from the execution units to selected locations in the register files, in response to write-to-register commands in the program instructions;
- g. data-transfer output means having its inputs coupled to the outputs of said I, J and K execution units and further having its outputs coupled to the memory for passing selected operands from the processor to the memory, in response to write-to-memory commands carried in the program instructions;
- and,
- h. a program evaluation unit coupled to said I, J, and K register files and to said data transfer input means for passing commands in the program instructions to the register files, the execution units, the broadcast buffers, the data-return means, and the data-transfer input means and output means.
6 more elements
A process for processing a series of program instructions and data for carrying out vector/vector and scalar/vector arithmetic operations, comprising:
- a. a memory for storing the program instructions and data and for storing the results of arithmetic operations performed in accordance with the program instructions;
- b. a data transfer input means for receiving the series of program instructions and data from the memory;
- c. I, J, and K register files coupled to said data transfer input means of receiving operands therefrom, each containing a plurality of registers for storing scalar values for the components of a plurality of three-dimensional vectors;
- d. I, J, and K execution units coupled to said I, J, and K register files for performing arithmetic operations on operands placed in the execution units;
- e. I, J, and K operand pathways connecting each I, J, and K register file, respectively, with the corresponding I, J, and K execution units, for transferring operands stored in selected register locations to the corresponding execution units, in response to data-fetch commands carried in the program instructions, each said I, J, and K operand pathways including a first and second data bus;
- f. first and second broadcast buffers connecting I and J operand pathways and J and K operand pathways, respectively, for passing operands between each pair of the operand pathways, in response to pathway exchange commands carried in the program instructions;
- g. data-return means coupled to said I, J, and K execution units and said I, J, and K register files for returning operands from the execution units to selected locations in the register files, in response to wire-to-register commands in the program instructions;
- h. data-transfer output means having its inputs coupled to the outputs of said I, J and K execution units and further having its outputs coupled to the memory for passing selected operands from the processor to the memory, in response to write-to-memory commands carried in the program instructions;
- and,
- i. a program evaluation unit coupled to said I, J, and K register files and to said data transfer input means for passing commands in the program instructions to the register files, the execution units, the broadcast buffers, the data-return means, and the data-transfer input means and output means.
7 more elements
Dependencies are inferred from the claim text.