Fully homomorphic encryption (fhe) operations on a unified fhe accelerator

A system comprising:

• a local memory to store instructions and/or data for a program;
• a scratchpad memory, coupled to the local memory, to store instructions and/or data for the program;
• and
• execution blocks, coupled to the scratchpad memory, to execute one or more mathematic and/or logical instructions of the program, wherein each execution block is to include a register file to store polynomial data and butterfly compute circuitry coupled to the register file, the butterfly compute circuitry to support a polynomial integer multiplication in response to an instance of a single instruction of a first type, wherein the instance of the single instruction is at least to include one or more fields for a register file address for a first source operand of the integer multiplication, one or more fields for a register file address for a second source operand of the integer multiplication, and one more fields for a register file address for a result of the integer multiplication, wherein the butterfly compute circuitry is to additionally support modular arithmetic operations.

A method comprising:

• decoding instructions of a plurality of threads of a program, wherein each thread is to be handled by a different set of physical resources;
• placing each decoded instruction into an instruction queue, of a plurality of instruction queues, dedicated to a particular set of the different sets of physical resources;
• streaming instructions from each instruction queue dedicated to a particular set of the different sets of physical resources;
• and
• independently executing the decoded instructions from each thread using its dedicated particular set of physical resources including butterfly compute circuitry, wherein at least one of the instructions is a polynomial integer multiplication instruction that is at least to include one or more fields for a register file address for a first source operand of the integer multiplication, one or more fields for a register file address for a second source operand of the integer multiplication, and one more fields for a register file address for a result of the integer multiplication, wherein the butterfly compute circuitry is to additionally support modular arithmetic operations.