SIMD datapath coupled to scalar/vector/address/conditional data register file with selective subpath scalar processing mode

A processor designed to operate in a plurality of modes for processing vector and scalar instructions, where a vector instruction identifies a single operation to be performed on a plurality of data elements, and a scalar instruction identifies a single operation to be performed on a single data element, comprising:

• one or more merged Single Instruction Stream, Multiple Data Stream (SIMD)/scalar register files, each for storing data directly usable as scalar data, vactor data, and conditional data
• one or more address register files, each for storing address information;
• a parallel vector unit coupled to receive data from the one or more merged SLMD/scalar register files and comprising a plurality of functional units configurable to operate in a vector operation mode and a scalar operation mode, the parallel vector unit includes means for tightly coupling a plurality of the functional units to perform an operation specified by a current instruction;
• wherein under a vector operation mode the parallel vector unit performs, in parallel, a single vector operation on a plurality of data elements, the operations performed on the plurality of data elements each being performed by a different functional unit of the parallel vector unit;
• and
• wherein under a scalar operation mode the parallel vector unit performs a scalar operation on a data element received from the one or more merged SIMD/scalar register files in a functional unit within the parallel vector unit.