G06F 9/30098
Register arrangements
Official title: {Register arrangements}
G06F9/30098 (Register arrangements) appears on 5,859 US grants and 5,742 published applications in this corpus.
Search patents in G06F- Granted patents
- 5,859
- Published applications
- 5,742
- Assignees
- 884
- Inventors
- 7,646
- Latest grant
- 6 Oct 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1976 | 2 | 0 |
| 1977 | 2 | 0 |
| 1978 | 3 | 0 |
| 1979 | 1 | 0 |
| 1980 | 1 | 0 |
| 1981 | 2 | 0 |
| 1982 | 3 | 0 |
| 1983 | 6 | 0 |
| 1984 | 3 | 0 |
| 1985 | 1 | 0 |
| 1986 | 4 | 0 |
| 1987 | 3 | 0 |
| 1988 | 5 | 0 |
| 1989 | 8 | 0 |
| 1990 | 8 | 0 |
| 1991 | 10 | 0 |
| 1992 | 17 | 0 |
| 1993 | 20 | 0 |
| 1994 | 26 | 0 |
| 1995 | 28 | 0 |
| 1996 | 56 | 0 |
| 1997 | 58 | 0 |
| 1998 | 112 | 0 |
| 1999 | 120 | 0 |
| 2000 | 128 | 0 |
| 2001 | 145 | 29 |
| 2002 | 91 | 110 |
| 2003 | 92 | 112 |
| 2004 | 86 | 190 |
| 2005 | 83 | 149 |
| 2006 | 117 | 123 |
| 2007 | 116 | 122 |
| 2008 | 114 | 178 |
| 2009 | 103 | 141 |
| 2010 | 140 | 112 |
| 2011 | 129 | 104 |
| 2012 | 96 | 172 |
| 2013 | 132 | 233 |
| 2014 | 156 | 207 |
| 2015 | 193 | 207 |
| 2016 | 249 | 267 |
| 2017 | 257 | 316 |
| 2018 | 229 | 233 |
| 2019 | 296 | 413 |
| 2020 | 330 | 462 |
| 2021 | 458 | 487 |
| 2022 | 461 | 398 |
| 2023 | 394 | 371 |
| 2024 | 354 | 256 |
| 2025 | 267 | 183 |
| 2026 | 144 | 167 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Subgroups
Granted patents
Recent patents
- Apparatus and method for booting an application processor6 Oct 2026US 12,755,021 B2Intel Corporation
- Processor embedded streaming buffer29 Sep 2026US 12,748,592 B2Intel Corporation
- Application programming interface to indicate a number of registers to be used by instructions29 Sep 2026US 12,748,599 B1NVIDIA Corporation
- Operating system-level assistive features for contextual privacy22 Sep 2026US 12,743,490 B2Google Inc.
- Technique for handling ordering constrained access operations15 Sep 2026US 12,737,185 B2Arm Limited
- Control method and chip8 Oct 2026US 2026/0310463 A1Smarter Silicon (Shanghai) Technologies Co., Ltd.
- Inserting null vectors into a stream of vectors8 Oct 2026US 2026/0310466 A1Texas Instruments Incorporated
- Display method, electronic device, and readable medium8 Oct 2026US 2026/0310491 A1Honor Device Co., Ltd.
- Hardware-Assisted Dynamic Register Allocation8 Oct 2026US 2026/0310610 A1MIPS Tech, LLC
- Compiler-automated collection element address compression and access1 Oct 2026US 2026/0299904 A1Zoho Corporation Private Limited
Most cited
By later US patents
- Packet processing system including a policy engine having a classification unit624US 6,157,955 AIntel Corporation · 2000
- Method and system for efficient matrix multiplication in a SIMD processor architecture531US 7,873,812 B12011
- Multiple address-space data processor with addressable register and context switching470US 5,201,039 AMitsubishi Denki Kabushiki Kaisha · 1993
- Running-min and running-max instructions for processing vectors using a base value from a key element of an input vector426US 8,417,921 B2Apple Inc. · 2013
- Processing architecture having a compare capability417US 7,028,170 B2Sun Microsystems, Inc. · 2006