Processing architecture having a compare capability
AssigneeSun Microsystems, Inc.
InventorAshley Saulsbury
Life of this patent
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Abstract
According to the invention, a processing core that executes a compare instruction is disclosed. The processing core includes a register file, comparison logic, decode logic, and a store path. Included in the register file are a number of general-purpose registers. The general-purpose registers include a first input operand register, a second input operand register and an output operand register. Comparison logic is coupled to the register file. The comparison logic tests for at least two of the following relationships: less than, equal to, greater than and no valid relationship. The decode logic selects the output operand register from the plurality of general-purpose registers. The store path extends between the comparison logic and the selected output operand register.
Claims20
A processing core that executes a compare instruction, the processing core comprising:
- a plurality of general-purpose registers comprising a first input operand register, a second input operand register and an output operand register;
- a register file comprising the plurality of general-purpose registers;
- comparison logic coupled to the register file, wherein:
- the comparison logic tests for at least two of a following relationships with the compare instruction alone:
- less than, equal to, greater than or no valid relationship,
- the comparison logic with the compare instruction alone produces a value, and
- the value has at least four states to represent the at least two relationships;
- decode logic, which selects the output operand register from the plurality of general-purpose registers;
- and
- a store path between the comparison logic and the selected output operand register, wherein the value is stored in the selected output operand register,
- wherein the compare instruction comprises a machine code instruction.
A method for performing a compare operation, the method comprising steps of:
- receiving a compare instruction comprising a machine code instruction;
- configuring first and second paths between a register file and comparison logic;
- configuring a third path between the comparison logic and the register file;
- comparing a first input operand and a second input operand with the compare operation alone, wherein the comparing step comprises step of:
- producing a result, which has at least four states to indicate at least two of a following mathematical relationships between the first input operand and the second input operand:
- less than, equal to, greater than, or no valid relationship;
- and
- coupling the result to a general-purpose register in the register file.
A method for executing a compare instruction in a processor, the method comprising steps of:
- issuing the compare instruction comprising a machine code instruction;
- comparing a first input operand and a second input operand to determine at least two mathematical relationships between the first and second input operands, wherein the compare instruction alone causes the comparing step;
- determining an output operand which has at least four states indicative of the at least two mathematical relationships;
- and
- storing the output operand in a general-purpose register of a register file, wherein the output operand alone indicates the at least two mathematical relationships between the first and second input operands.
Dependencies are inferred from the claim text.