Computing system having an accumulator register having entries having a bit width larger than a main register file

A processor for processing instructions, the processor comprising:

• a main physical register file having a plurality of main physical register file entries for storing main register data, each main physical register file entry having a main register bit field width for storing the main register data;
• one or more execution units including a dense math execution unit;
• at least one physical accumulator register file separate and distinct from the main physical register file and having a plurality of physical entries for storing accumulator register data, each physical accumulator register file entry of the at least one physical accumulator register file having an accumulator register bit field width that is wider than the main register bit field width of the plurality of main physical register file entries and wherein each physical entry in the at least one physical accumulator register file is mapped to a plurality of main physical register file entries,
• the processor configured to:
• write results of the dense math execution unit to the at least one physical accumulator register file;
• and
• write data from the at least one physical accumulator register file to the main physical register file.

A computing system for processing information, the computing system comprising:

• a main register file having a plurality of entries for storing main register data;
• one or more execution units including a dense math execution unit;
• at least one accumulator register file having a plurality of accumulator register file entries for storing accumulator register data, wherein the at least one accumulator register file is associated with the dense math execution unit,
• the computing system configured to:
• prime at least one accumulator register file entry to receive data, wherein the at least one accumulator register file entry is at least one of the plurality of accumulator register file entries of the at least one accumulator register file associated with the dense math execution unit;
• mark, in response to priming the at least one accumulator register file entry to receive data, one or more main register file entries mapped to the at least one primed accumulator register file entry as busy;
• and
• process data in the dense math execution unit where results of the dense math execution unit are written to the at least one primed accumulator register file entry.