G06F 2205/102
Avoiding metastability, i.e. preventing hazards
Official title: Avoiding metastability, i.e. preventing hazards, e.g. by using Gray code counters
G06F2205/102 (Avoiding metastability, i.e. preventing hazards) appears on 71 US grants and 33 published applications in this corpus.
Search patents in G06F- Granted patents
- 71
- Published applications
- 33
- Assignees
- 48
- Inventors
- 133
- Latest grant
- 2 Dec 2025
Filings by year
| Year | Granted patents | Published applications |
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| 1980 | 1 | 0 |
| 1981 | 0 | 0 |
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| 1983 | 0 | 0 |
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| 1985 | 0 | 0 |
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| 2001 | 2 | 0 |
| 2002 | 9 | 2 |
| 2003 | 2 | 5 |
| 2004 | 6 | 6 |
| 2005 | 8 | 6 |
| 2006 | 1 | 0 |
| 2007 | 4 | 1 |
| 2008 | 0 | 1 |
| 2009 | 2 | 1 |
| 2010 | 2 | 1 |
| 2011 | 0 | 0 |
| 2012 | 0 | 1 |
| 2013 | 1 | 2 |
| 2014 | 3 | 1 |
| 2015 | 2 | 1 |
| 2016 | 2 | 4 |
| 2017 | 2 | 0 |
| 2018 | 1 | 0 |
| 2019 | 1 | 1 |
| 2020 | 1 | 0 |
| 2021 | 0 | 0 |
| 2022 | 0 | 0 |
| 2023 | 0 | 0 |
| 2024 | 0 | 0 |
| 2025 | 1 | 0 |
By publication year. Applications have been published since 2001.
Recent patents
- Gray code counter enabled to increment by greater than one2 Dec 2025US 12,487,631 B1Synopsys, Inc.
- Binary-to-gray conversion circuit, related FIFO memory, integrated circuit and method28 Apr 2020US 10,635,394 B2STMicroelectronics S,r.l.
- Systems and methods for gray coding based error correction in an asynchronous counter22 Jan 2019US 10,187,082 B1Marvell International Ltd.
- Data transfer between clock domains21 Aug 2018US 10,055,193 B2Nordic Semiconductor ASA
- Bi-synchronous electronic device with burst indicator and related methods8 Aug 2017US 9,727,306 B2STMicroelectronics S,r.l.
- Binary-to-gray conversion circuit, related fifo memory, integrated circuit and method29 Aug 2019US 2019/0265947 A1STMicroelectronics S,r.l.
- Asynchronous fifo buffer with johnson code write pointer5 May 2016US 2016/0124889 A1NXP USA, Inc.
- Bi-synchronous electronic device with burst indicator and related methods7 Apr 2016US 2016/0099031 A1STMicroelectronics S,r.l.
- Bi-synchronous electronic device and fifo memory circuit with jump candidates and related methods7 Apr 2016US 2016/0099032 A1STMicroelectronics S,r.l.
- Method and apparatus for asynchronous fifo circuit4 Feb 2016US 2016/0035399 A1Texas Instruments Incorporated
Most cited
By later US patents
- Method and apparatus for bit-to-bit timing correction of a high speed memory bus137US 6,662,304 B2Micron Technology, Inc. · 2003
- Predictive status flag generation in a first-in first-out (FIFO) memory device method and apparatus97US 5,506,809 ASharp Kabushiki Kaisha · 1996
- Synchronizing data operations across a synchronization boundary between different clock domains using two-hot encoding94US 6,366,530 B1LSI Logic Corporation · 2002
- FIFO memory system and method with improved determination of full and empty conditions and amount of data stored83US 6,434,642 B1Xilinx, Inc. · 2002
- Memory controller and method determining empty/full status of a FIFO memory using gray code counters75US 5,426,756 AS3 Incorporated · 1995